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S3C2440X Datasheet(PDF) 47 Page - Samsung semiconductor |
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S3C2440X Datasheet(HTML) 47 Page - Samsung semiconductor |
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47 / 429 page  2003.09.25 Preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available Specifications and information herein are subject to change without notice. MEMORY CONTROLLER S3C2440X RISC MICROPROCESSOR 5-6 nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, the S3C2440X will respond by lowering nXBACK. If nXBACK=L, the address/data bus and memory control signals are in Hi-Z state as shown in Table 1-1. When nXBREQ is de-asserted, the nXBACK will also be de-asserted. HCLK SCKE, A[24:0] D[31:0], nGCS nOE,nWE nWBE nXBREQ nXBACK SCLK 1clk Figure 5-3. S3C2440X nXBREQ/nXBACK Timing Diagram |
Similar Part No. - S3C2440X |
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Similar Description - S3C2440X |
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