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S3C2440X Datasheet(PDF) 44 Page - Samsung semiconductor

Part # S3C2440X
Description  16/32-bit RISC microprocessor
Download  429 Pages
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Manufacturer  SAMSUNG [Samsung semiconductor]
Direct Link  http://www.samsung.com/Products/Semiconductor
Logo SAMSUNG - Samsung semiconductor

S3C2440X Datasheet(HTML) 44 Page - Samsung semiconductor

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2003.09.25
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
S3C2440X RISC MICROPROCESSOR
MEMORY CONTROLLER
DEC.13, 2002
5-3
FUNCTION DESCRIPTION
BANK0 BUS WIDTH
The data bus of BANK0 (nGCS0) should be configured in width as one of 16-bit and 32-bit ones. Because the
BANK0 works as the booting ROM bank (map to 0x0000_0000), the bus width of BANK0 should be determined
before the first ROM access, which will depend on the logic level of OM[1:0] at Reset.
OM1 (Operating Mode 1)
OM0 (Operating Mode 0)
Booting ROM Data width
0
0
Nand Flash Mode
0
1
16-bit
1
0
32-bit
1
1
Test Mode
MEMORY (SROM/SDRAM) ADDRESS PIN CONNECTIONS
MEMORY ADDR. PIN
S3C2440X ADDR.
@ 8-bit DATA BUS
S3C2440X ADDR.
@16-bitDATA BUS
S3C2440X ADDR.
@ 32-bit DATA BUS
A0
A0
A1
A2
A1
A1
A2
A3
...
. . .
...
...


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