Electronic Components Datasheet Search |
|
PC8477BVF-1 Datasheet(PDF) 33 Page - National Semiconductor (TI) |
|
|
|
PC8477BVF-1 Datasheet(HTML) 33 Page - National Semiconductor (TI) |
33 / 54 page 50 Functional Description (Continued) TLF11332 – 5 FIGURE 5-1 PC8477B Data Separator Block Diagram 54 DATA SEPARATOR The internal data separator consists of an analog PLL and its associated circuitry The PLL synchronizes the raw data signal read from the disk drive The synchronized signal is used to separate the encoded clock and data pulses The data pulses are deserialized into bytes and then sent to the m P by the controller The main PLL consists of five main components a phase comparator a charge pump a filter a voltage controlled oscillator (VCO) and a programmable divider The phase comparator detects the difference between the phase of the divider’s output and the phase of the raw data being read from the disk This phase difference is converted to a cur- rent by the charge pump which either charges or discharg- es one of three filters which is selected based on the data rate The resulting voltage on the filter changes the frequen- cy of the VCO and the divider output to reduce the phase difference between the input data and the divider’s output The PLL is ‘‘locked’’ when the frequency of the divider is exactly the same as the average frequency of the data read from the disk A block diagram of the data separator is shown in Figure 5-1 To ensure optimal performance the data separator incorpo- rates several additional circuits The quarter period delay line is used to determine the center of each bit cell and to disable the phase comparator when the raw data signal is missing a clock or data pulse in the MFM or FM pattern A secondary PLL is used to automatically calibrate the quarter period delay line The secondary PLL also calibrates the center frequency of the VCO To eliminate the logic associated with controlling multiple data rates the PC8477B supports each of the four data rates (250 300 500 kbs and 1 Mbs) with a separate optimized internal filter The appropriate filter for each data rate is automatically switched into the data separator circuit when the data rate is selected via the Data Rate Select or Configuration Control Register These filters have been opti- mized through lab experimentation and are designed into the controller to reduce the external component cost asso- ciated with the floppy controller The PC8477B has a dy- namic window margin and lock range performance capable of handling a wide range of floppy disk drives Also the data separator will work well under a variety of conditions includ- ing the high motor speed fluctuations of floppy compatible tape drives The controller takes best advantage of the internal analog data separator by implementing a sophisticated read algo- rithm The ID search algorithm shown in Figure 5-2 en- hances the PLL’s lock characteristics by forcing the PLL to relock to the crystal reference frequency any time the data separator attempts to lock to a non-preamble pattern This algorithm ensures that the PLL is not thrown way out of lock by write splices or bad data fields 33 |
Similar Part No. - PC8477BVF-1 |
|
Similar Description - PC8477BVF-1 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |