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PC8477BVF-1 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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PC8477BVF-1 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 54 page  30 Register Description (Continued) 34 DRIVE REGISTER (TDR) ReadWrite This register is used to assign a particular drive number with the tape drive support mode of the data separator All other logical drives are assigned floppy drive support with the data separator Any future reference to the assigned tape drive will invoke tape drive support The TDR is unaffected by a software reset TDR D7 D6 D5 D4 D3 D2 D1 D0 DESC XXXXXX TAPE TAPE SEL1 SEL0 RESET NA NA NA NA NA NA 0 0 COND D7 – D2 Reserved These bits are ignored when written to and are TRI-STATE when read D1 – D0 Tape Select 10 These two bits assign a logical drive number to be a tape drive Drive 0 is not available as a tape drive and is reserved as the floppy disk boot drive See Table 3-3 for the tape drive assignment values TABLE 3-3 Tape Drive Assignment Values TAPESEL1 TAPESEL0 DRIVE SELECTED 0 0 None 01 1 10 2 11 3 35 MAIN STATUS REGISTER (MSR) Read Only The read only Main Status Register indicates the current status of the disk controller The Main Status Register is always available to be read One of its functions is to control the flow of data to and from the Data Register (FIFO) The Main Status Register indicates when the disk controller is ready to send or receive data through the Data Register It should be read before each byte is transferred to or from the Data Register except during a DMA transfer No delay is required when reading this register after a data transfer After a hardware or software reset or recovery from a pow- er down state the Main Status Register is immediately avail- able to be read by the mP It will contain a value of 00 hex until the oscillator circuit has stabilized and the internal reg- isters have been initialized When the PC8477B is ready to receive a new command it will report an 80 hex to the mP The system software can poll the MSR until it is ready The worst case time allowed for the MSR to report an 80 hex value (RQM set) is 25 ms after reset or power up MSR D7 D6 D5 D4 D3 D2 D1 D0 DESC RQM DIO NON CMD DRV3 DRV2 DRV1 DRV0 DMA PROG BUSY BUSY BUSY BUSY RESET 0 0 0 0 0000 COND D7 Request for Master Indicates that the control- ler is ready to send or receive data from the mP through the FIFO This bit is cleared immediate- ly after a byte transfer and will become set again as soon as the disk controller is ready for the next byte During a Non-DMA Execution phase the RQM indicates the status of the in- terrupt pin D6 Data IO (Direction) Indicates whether the controller is expecting a byte to be written to (0) or read from (1) the Data Register D5 Non-DMA Execution Indicates that the con- troller is in the Execution Phase of a byte trans- fer operation in the Non-DMA mode Used for multiple byte transfers by the mP in the Execu- tion Phase through interrupts or software poll- ing D4 Command in Progress This bit is set after the first byte of the Command Phase is written This bit is cleared after the last byte of the Result Phase is read If there is no Result Phase in a command the bit is cleared after the last byte of the Command Phase is written D3 Drive 3 Busy Set after the last byte of the Command Phase of a Seek or Recalibrate com- mand is issued for drive 3 Cleared after reading the first byte in the Result Phase of the Sense Interrupt Command for this drive D2 Drive 2 Busy Same as above for drive 2 D1 Drive 1 Busy Same as above for drive 1 D0 Drive 0 Busy Same as above for drive 0 36 DATA RATE SELECT REGISTER (DSR) Write Only This write only register is used to program the data rate amount of write precompensation power down mode and software reset The data rate is programmed via the CCR not the DSR for PC-AT and PS2 Model 30 and MicroChan- nel applications Other applications can set the data rate in the DSR The data rate of the floppy controller is deter- mined by the most recent write to either the DSR or CCR The DSR is unaffected by a software reset A hardware re- set will set the DSR to 02 (hex) which corresponds to the default precompensation setting and 250 kbs DSR D7 D6 D5 D4 D3 D2 D1 D0 DESC SW LOW 0 PRE- PRE- PRE- DRATE1 DRATE0 RESET PWR COMP2 COMP1 COMP0 RESET 0 0 0 000 1 0 COND D7 Software Reset A 1 in this bit location will re- set the part similar to the DOR RESET (D2) ex- cept that this software reset is self-clearing D6 Low Power A 1 to this bit will put the controller into the Manual Low Power mode The oscilla- tor and data separator circuits will be turned off Manual Low Power can also be accessed via the Mode command The chip will come out of low power after a software reset or access to the Data Register or Main Status Register 11 |
Similar Part No. - PC8477BVF-1 |
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Similar Description - PC8477BVF-1 |
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