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PC8477BVF-1 Datasheet(PDF) 10 Page - National Semiconductor (TI) |
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PC8477BVF-1 Datasheet(HTML) 10 Page - National Semiconductor (TI) |
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10 / 54 page  30 Register Description (Continued) 321 SRBPS2 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC 1 1 DR0 WDATA RDATA WGATE MTR1 MTR0 RESET NA NA 0 0 0 0 0 0 COND D7 Reserved Always 1 D6 Reserved Always 1 D5 Drive Select 0 Reflects the status of the Drive Select 0 bit in the DOR (address 2 bit 0) This bit is cleared after a hardware reset not a soft- ware reset D4 Write Data Every inactive edge transition of the WDATA disk interface output causes this bit to change states D3 Read Data Every positive edge transition of the RDATA disk interface output causes this bit to change states D2 Write Gate Active high status of the WGATE disk interface output D1 Motor Enable 1 Active high status of the MTR1 disk interface output Low after a hard- ware reset unaffected by a software reset D0 Motor Enable 0 Active high status of the MTR0 disk interface output Low after a hard- ware reset unaffected by a software reset 322 SRBModel 30 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC DRV2 DR1 DR0 WDATA RDATA WGATE DR3 DR2 RESET NA 1 1 0 0 0 1 1 COND D7 2nd Drive Installed Active low status of the DRV2 disk interface input D6 Drive Select 1 Active low status of the DR1 disk interface output D5 Drive Select 0 Active low status of the DR0 disk interface output D4 Write Data Active high status of latched WDATA signal This bit is latched by the inac- tive going edge of WDATA and is cleared by a read from the DIR This bit is not gated by WGATE D3 Read Data Active high status of latched RDATA signal This bit is latched by the inactive going edge of RDATA and is cleared by a read from the DIR D2 Write Gate Active high status of latched WGATE signal This bit is latched by the active going edge of WGATE and is cleared by a read from the DIR D1 Drive Select 3 Active low status of the DR3 disk interface output D0 Drive Select 2 Active low status of the DR2 disk interface output 33 DIGITAL OUTPUT REGISTER (DOR) ReadWrite The DOR controls the drive select and motor enable disk interface outputs enables the DMA logic and contains a software reset bit The contents of the DOR are set to 00 (hex) after a hardware reset and are unaffected by a soft- ware reset The DOR can be written to at any time DOR D7 D6 D5 D4 D3 D2 D1 D0 DESC MTR3 MTR2 MTR1 MTR0 DMAEN RESET DRIVE DRIVE SEL 1 SEL 0 RESET 0000 0 0 0 0 COND D7 Motor Enable 3 This bit controls the MTR3 disk interface output A1in this bit causes the MTR3 pin to go active The actual level of MTR3 depends on the state of the INVERT pin D6 Motor Enable 2 Same function as D7 except for MTR2 D5 Motor Enable 1 Same function as D7 except for MTR1 D4 Motor Enable 0 Same function as D7 except for MTR0 D3 DMA Enable This bit has two modes of opera- tion PC-AT mode or Model 30 mode Writing a 1 to this bit will enable the DRQ DAK INT and TC pins Writinga0to this bit will TRI-STATE DRQ and INT and disable DAK and TC This bit is a 0 after a reset when in these modes PS2 mode This bit is reserved and the DRQ DAK INT and TC pins will always be enabled During a reset the DRQ DAK and INT lines will remain enabled and D3 will be a 0 D2 Reset Controller Writinga0to this bit resets the controller It will remain in the reset condi- tion untila1is written to this bit A software reset does not affect the DSR CCR and other bits of the DOR A software reset will affect the Configure and Mode command bits (see Sec- tion 40 Command Set Description) The mini- mum time that this bit must be low is 100 ns Thus toggling the Reset Controller bit during consecutive writes to the DOR is an acceptable method of issuing a software reset D1 – D0 Drive Select These two bits are binary encod- ed for the four drive selects DR0 – DR3 so that only one drive select output is active at a time The actual level of the drive select outputs is determined by the state of the INVERT pin It is common programming practice to enable both the mo- tor enable and drive select outputs for a particular drive Table 3-2 below shows the DOR values to enable each of the four drives TABLE 3-2 Drive Enable Values Drive DOR Value 0 1C (Hex) 12D 24E 38F 10 |
Similar Part No. - PC8477BVF-1 |
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Similar Description - PC8477BVF-1 |
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