Symbol

PLCC

PQFP

IO

Function

Pin

Pin

PLL0

39

(Note 1)

Phase Locked Loop 01

No connects These pins can be tied high or low with no affect

PLL1

40

on the data separator performance

RD

441

I

Read

Active low input to signal a read from the controller to the microprocessor

RDATA

41

13

I

Read Data

This input is the raw serial data read from the disk drive

RESET

32

6

I

Reset

Active high input that resets the controller to the idle state and resets all disk

interface outputs to their inactive states The DOR DSR CCR Mode command

Configure command and Lock command parameters are cleared to their default values

The Specify command parameters are not affected

STEP

55

25

O

Step

This output signal issues pulses to the disk drive at a software programmable rate

to move the head during a seek operation

TC

25

59

I

Terminal Count

Control signal from the DMA controller to indicate the termination of a

DMA transfer TC is accepted only when DACK is active TC is active high in PC-AT and

Model 30 modes and active low in PS2 mode

TRK0

2

39

I

Track 0

This input indicates to the controller that the head of the selected disk drive is at

track zero

18

30

Voltage

60

37

68

53

WDATA

53

23

O

Write Data

This output is the write precompensated serial data that is written to the

selected disk drive Precompensation is software selectable

WGATE

52

22

O

Write Gate

This output signal enables the write circuitry of the selected disk drive

WGATE has been designed to prevent glitches during power up and power down This

prevents writing to the disk when power is cycled

WP

1

38

I

Write Protect

This input indicates that the disk in the selected drive is write protected

WR

542

I

Write

Active low input to signal a write from the microprocessor to the controller

XTAL1CLK

33

7

I

Crystal1Clock

One side of an external 24 MHz crystal is attached here If a crystal is

not used a TTL or CMOS compatible clock is connected to this pin

XTAL2

34

8

I

Crystal2

One side of an external 24 MHz crystal is attached here This pin is left

unconnected if an external clock is used

Note 1

When converting the 68 pin PLCC to a 60 pin PQFP eight pins were removed The following signals were affected in this conversion process

1 NC (No Connect) signals on pins 42 and 43 of the 68 pin PLCC were converted to GND (Ground) signals on pins 14 and 15 of the 60 pin PQFP

respectively

2 NC (No Connect) signals on pins 44 and 47 of the 68 pin PLCC were removed for the 60 pin PQFP

3 HIFIL (pin 38) and LOFIL (pin 37) of the 68 pin PLCC were removed for the 60 pin PQFP

4 PLL0 (pin 39) and PLL1 (pin 40) of the 68 PLCC were converted to GND (ground) signals on the PQFP (pins 11 and 12 respectively)

5 The GND (ground) signals on pins 9 12 21 and 65 of the 68 pin PLCC are not available for the 60 pin PQFP These signals are tied to ground internally

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