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PC8477BVF-1 Datasheet(PDF) 47 Page - National Semiconductor (TI) |
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PC8477BVF-1 Datasheet(HTML) 47 Page - National Semiconductor (TI) |
47 / 54 page 70 Reference Section (Continued) 72 PC8477B ENHANCEMENTS VS 82077AA The enhancements listed below are additional functions of the PC8477B that the 82077AA does not have and do not affect the compatibility between the two floppy controllers Commands The following are PC8477B commands not supported by the 82077AA Mode Command Controls several enhanced fea- tures of the PC8477B such as Implied Seeks Low Power mode additional FIFO modes and DENSEL encoding The Mode command parameters are de- fault to 82077AA compatible states and will be un- affected by 82077AA-based software that does not recognize the existence of a Mode command See the PC8477B data sheet for more details NSC Command This one byte command is used to identify the PC8477B in the system Other floppy controllers will return an 80 hex (invalid command) while the PC8477B will return a value of 73 hex (the lower four bits are reserved to indicate revision up- dates in the part) Set Track Command This command allows the user to program the value of any of the four Present Track Registers corresponding to the four logical drives FIFO Operation The PC8477B FIFO is compatible with the 82077AA FIFO with the addition of a Non-Burst mode The default setting when the FIFO is enabled is the 82077AA compatible Burst mode The Non-Burst mode is enabled via the Mode com- mand The Non-Burst mode will pulse the DRQ or INT sig- nals during a burst transfer to or from the FIFO For both the Burst and Non-Burst modes with the FIFO en- abled no external circuitry is required with the PC8477B during DMA verify transfers During verify operations the DMA controller will assert the DACK signal without a RD signal in response to a DRQ from the floppy controller The 82077AA however requires external circuitry to create the RD signal during DMA verify operations with its FIFO en- abled in order to work successfully without an overrun error The published Intel bug fix for the 82077AA can only be used for motherboard applications and not for add-in boards The PC8477B does not have this problem Also because of the byte counter in the PC8477B design the DRQ or INT signal will be deasserted when the last byte of a sector is written to the FIFO during the execution phase of a write or format operation The 82077AA does not deas- sert DRQ or INT until the last byte has been read out of the FIFO This will cause a delay in the deassertion of DRQ or INT of up to 16 byte times resulting in extra bytes trans- ferred to the floppy controller The PC8477B does not have this problem Data Separator The PC8477B data separator’s performance meets that of the 82077AA’s However there are no dual modes in the PC8477B data separator whereas the 82077AA data sepa- rator has an internal floppy drive mode and an internal tape drive mode This singular mode design of the PC8477B data separator eliminates the need for hardware or software con- trol and provides for more consistent performance The PC8477B data separator is designed to work with the strict- est motor speed and bit jitter requirements of both floppy and tape drives Low Power Mode The typical measured low power current for the PC8477B (analog and digital) is 1 mA The typical measured low pow- er current for the 82077AA is 2 mA – 3 mA The PC8477A supports the 82077AA manual low power mode by writing to the Low Power bit (D6) in the Data Rate Select register The low power mode is turned off by issuing a reset to the chip whereupon re-initialization is necessary In addition the PC8477B supports a manual low power AND automatic low power mode via the Mode command Manual low power must be invoked every time the low power mode is desired Automatic low power mode need only be invoked once during initialization and then low power is entered whenever the floppy controller is idle As mentioned the 82077AA and PC8477B will exit the low power mode after a reset The PC8477B will also exit the low power mode after any read or write to the Main Status Register or Data Register In this way the part can exit low power cleanly without requiring additional software initializa- tion This feature gives the PC8477B an advantage in that once software has initialized it for automatic low power no additional software modifications are necessary and the chip will power down whenever it is idle Even for manual low power mode via the DSR or Mode command the PC8477B can return to normal mode without re-initialization as required for the 82077 Reset Pulse Width The PC8477B software reset pulse width is 100 ns mini- mum This means that software can issue two consecutive writes to the Digital Output Register of the PC8477B to tog- gle the Reset Controller bit (D2) without intervening delay This specification is significantly better than the 82077AA minimum software reset pulse width which is specified as 35 ms (worst case at the 250 kbs data rate) When using an external pull-up or pull-down 10 kX resistor on the MFM pin the hardware reset pulse width is also 100 ns minimum for the PC8477B The minimum hardware reset pulse width for the 82077AA is 71 ms Again the PC8477B specification is much better allowing the system reset pulse to be very short Tape Drive Register The PC8477B will support reads and writes to this register just as the 82077AA does However the PC8477B will not use the information written to the Tape Drive Register to alter the state of the Data Separator That is there is only one mode of the internal PC8477B data separator a high performance mode that will support the requirements for all floppy and tape drives Implied Seeks The PC8477B supports our popular DP8473 method as well as the 82077AA method of implementing Implied Seeks The DP8473 method is to set a bit in the Mode command for enabling Implied Seeks and then set the Implied Seek bit if desired in the Read Write or Scan commands The 82077AA method is to set the EIS bit (enable implied seeks) in the Configure command and then Implied Seeks will al- ways be enabled for Read Write and Verify commands 47 |
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