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PC8477BV-1 Datasheet(PDF) 15 Page - National Semiconductor (TI) |
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PC8477BV-1 Datasheet(HTML) 15 Page - National Semiconductor (TI) |
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15 / 54 page  40 Command Set Description The following is a table of the PC8477B command set Each command contains a unique first command byte called the opcode byte which will identify to the controller how many command bytes to expect If an invalid command byte is issued to the controller it will immediately go into the Result Phase and the status will be 80 (hex) which signifies Invalid Command 41 COMMAND SET SUMMARY CONFIGURE Command Phase 0 0 0 1 0011 0 0 0 0 0000 0 EIS FIFO POLL THRESH PRETRK Execution Phase Internal registers written No Result Phase DUMPREG Command Phase 00001110 Execution Phase Internal registers read Result Phase PTR Drive 0 PTR Drive 1 PTR Drive 2 PTR Drive 3 Step Rate Time Motor Off Time Motor On Time DMA Sectors per TrackEnd of Track LOCK 0 DC3 DC2 DC1 DC0 GAP WG 0 EIS FIFO POLL THRESH PRETRK Note Sectors per Track parameter returned if last command issued was Format End of Track parameter returned if last command issued was Read or Write FORMAT TRACK Command Phase 0 MFM 0 0 1 1 0 1 X X XXXHDDR1 DR0 Bytes per Sector Sectors per Track Format Gap Data Pattern Execution Phase System transfers four ID bytes (track head sector bytessector) per sector to the floppy control- ler via DMA or Non-DMA modes The entire track is format- ted The data block in the Data Field of each sector is filled with the data pattern byte Result Phase Status Register 0 Status Register 1 Status Register 2 Undefined Undefined Undefined Undefined INVALID Command Phase Invalid Op Codes Result Phase Status Register 0 (80 hex) LOCK Command Phase LOCK 0 0 1 0 1 0 0 Execution Phase Internal register is written Result Phase 0 0 0 LOCK 0 0 0 0 MODE Command Phase 00 0 0 0 0 0 1 TMR IAF IPS 0 LOW PWR 1 ETR FWR FRD BST R255 0 0 0 0 DENSEL BFR WLD Head Settle 00 0 0 0 RG O PU Execution Phase Internal registers are written No Result Phase NSC Command Phase 00011000 Result Phase 01110011 PERPENDICULAR MODE Command Phase 0 0 0100 1 0 OW 0 DC3 DC2 DC1 DC0 GAP WG Execution Phase Internal registers are written No Result Phase 15 |
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