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PC8477BV-1 Datasheet(PDF) 13 Page - National Semiconductor (TI) |
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PC8477BV-1 Datasheet(HTML) 13 Page - National Semiconductor (TI) |
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13 / 54 page  30 Register Description (Continued) 381 DIRPC-AT Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC DSKCHG X X X X X X X RESET NA NA NA NA NA NA NA NA COND D7 Disk Changed Active high status of DSKCHG disk interface input independent of INVERT value D6 – D0 Undefined TRI-STATE Used by hard disk con- troller status register 382 DIRPS2 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC DSKCHG 1 1 1 1 DRATE1 DRATE0 HIGH DEN RESET NA NA NA NA NA NA NA 1 COND D7 Disk Changed Active high status of DSKCHG disk interface input independent of INVERT value D6 – D3 Reserved Always 1 D2 – D1 Data Rate Select 10 These bits indicate the status of the DRATE1 – 0 bits programmed through the DSRCCR D0 High Density This bit is low when the 1 Mbs or 500 kbs data rate is chosen and high when the 300 kbs or 250 kbs data rate is chosen This bit is independent of the IDENT or INVERT value 383 DIRModel 30 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC DSKCHG 0 0 0 DMAEN NOPRE DRATE1 DRATE0 RESET NA 0 0 0 0 0 1 0 COND D7 Disk Changed Active low status of DSKCHG disk interface input independent of INVERT value D6 – D4 Reserved Always 0 D3 DMA Enable Active high status of the DMAEN bit in the DOR D2 No Precompensation Active high status of the NOPRE bit in the CCR D1 – D0 Data Rate Select 10 These bits indicate the status of the DRATE1 – 0 bits programmed through the DSRCCR 39 CONFIGURATION CONTROL REGISTER (CCR) Write Only This is the write only data rate register commonly used in PC-AT applications This register is not affected by a soft- ware reset and is set to 250 kbs after a hardware reset The data rate of the floppy controller is determined by the last write to either the CCR or DSR 391 CCRPC-AT and PS2 Modes D7 D6 D5 D4 D3 D2 D1 D0 DESC 0 0 0 0 0 0 DRATE1 DRATE0 RESET NA NA NA NA NA NA 1 0 COND D7 – D2 Reserved Should be set to 0 D1 – D0 Data Rate Select 10 These bits determine the data rate of the floppy controller See Table 3-6 for the appropriate values 392 CCRModel 30 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC 0 0 0 0 0 NOPRE DRATE1 DRATE0 RESET NA NA NA NA NA 0 1 0 COND D7 – D3 Reserved Should be set to 0 D2 No Precompensation This bit can be set by software but it has no functionality It can be read by bit D2 of the DIR when in the Model 30 register mode Unaffected by a software reset D1 – D0 Data Rate Select 10 These bits determine the data rate of the floppy controller See Table 3-6 for the appropriate values 310 RESULT PHASE STATUS REGISTERS The Result Phase of a command contains bytes that hold status information The format of these bytes are described below Do not confuse these status bytes with the Main Status Register which is a read only register that is always valid The Result Phase status registers are read from the Data Register (FIFO) only during the Result Phase of certain commands (see Section 41 Command Set Summary) The status of each register bit is indicated when the bit is a 1 3101 Status Register 0 (ST0) D7 D6 D5 D4 D3 D2 D1 D0 DESC IC IC SE EC 0 HDS DS1 DS0 RESET 00 0 0 0 0 0 0 COND D7 – D6 Interrupt Code 00 e Normal Termination of Command 01 e Abnormal Termination of Command Exe- cution of command was started but was not successfully completed 10 e Invalid Command Issued Command is- sued was not recognized as a valid com- mand 11 e Internal drive ready status changed state during the drive polling mode Only occurs after a hardware or software reset D5 Seek End Seek Relative Seek or Recalibrate command completed by the controller (Used during a Sense Interrupt command) D4 Equipment Check After a Recalibrate com- mand Track 0 signal failed to occur (Used dur- ing Sense Interrupt command) D3 Not Used Always 0 13 |
Similar Part No. - PC8477BV-1 |
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Similar Description - PC8477BV-1 |
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