 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PC8477BV-1 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC8477BV-1 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
|
|
6 / 54 page  20 Pin Description Symbol PLCC PQFP IO Function Pin Pin A0 7 44 I Address These address lines from the microprocessor determine which internal FDC A1 8 45 register is accessed See TABLE 3-1 in the Register Description section A0 – A2 are don’t A2 10 46 cares during a DMA transfer AVCC 46 17 Analog Supply This pin is the 5V supply for the analog data separator CS 643 I Chip Select Active low input from address decoder used to enable the RD and WR inputs during register IO Should be held inactive during DMA transfers D0 11 47 IO Data Bi-directional data lines to the microprocessor D0 is the LSB and D7 is the MSB D1 13 48 These signals all have 12 mA buffered outputs D2 14 49 D3 15 50 D4 17 52 D5 19 54 D6 20 55 D7 22 56 DACK 340 I DMA Acknowledge Active low input to acknowledge the DMA request and enable the RD and WR inputs during a DMA transfer DACK should be held inactive high during normal read or write accesses when CS is active When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode DAK is always enabled and bit D3 of the DOR is reserved DENSEL 49 19 O Density Select Indicates when a high density data rate (500 kbs or 1 Mbs) or a low density data rate (250 or 300 kbs) has been selected DENSEL is active high for high density (525 drives) when IDENT is high and active low for high density (35 drives) when IDENT is low DENSEL is also programmable via the Mode command (see Section 426) DIR 56 26 O Direction This output determines the direction of the head movement (active e step in inactive e step out) during a seek operation During read or writes DIR will be inactive DR0 58 28 O Drive Select 0 – 3 These are the decoded drive select outputs that are controlled by Digital DR1 62 32 Output Register bits D0 D1 The Drive Select outputs are gated by DOR bits 4 – 7 DR2 64 34 DR3 67 36 DRATE0 28 2 O Data Rate 01 These outputs reflect the currently selected data rate (bits 0 and 1 in the DRATE1 29 3 CCR or the DSR whichever was written to last) These pins are totem-pole buffered outputs (6 mA sink 4 mA source) DRQ 24 58 O DMA Request Active high output to signal the DMA controller that a data transfer is needed When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode DRQ is always enabled and bit D3 of the DOR is reserved DRV2 30 4 I Drive2 This input indicates whether a second disk drive has been installed The state of this pin is available from Status Register A in PS2 mode DSKCHG 31 5 I Disk Change The input indicates if the drive door has been opened The state of this pin is available from the Digital Input register This pin can also be configured as the RGATE data separator diagnostic input via the Mode command (see Section 426) GND 9 12 10 11 Ground 16 21 12 14 36 50 15 20 54 59 24 29 65 51 GNDA 45 16 Analog Ground This is the analog ground for the data separator 6 |
Similar Part No. - PC8477BV-1 |
|
Similar Description - PC8477BV-1 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
