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PC8477BV-1 Datasheet(PDF) 51 Page - National Semiconductor (TI) |
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PC8477BV-1 Datasheet(HTML) 51 Page - National Semiconductor (TI) |
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51 / 54 page  70 Reference Section (Continued) 74 SOFTWARE INITIALIZATION SEQUENCE Following power up the system will issue a hardware reset to the PC8477B This will put the internal registers and cir- cuitry into a known state after which the software initializa- tion sequence can begin End Reset The first task is to bring the PC8477B out of the reset state by writing 0CH to the DOR register The software should then poll the MSR until 80H is returned At this point the controller is ready to begin processing com- mands Service Ready Changed State Interrupt Once an inter- rupt is received the software should issue 4 SENSE INTER- RUPT commands for each of the 4 logical drives This is due to the fact that after a reset drive polling is enabled by default Set Data Rate The data rate should be set via a write to the CCR register The default state is 250 kbs following reset Configure the FIFO The default setting is with the FIFO disabled If the perpendicular format is to be supported the FIFO will need to be enabled due to the higher data rates used The FIFO threshold level should be set based on the DMA response time of the system A lower value of THRESH corresponds to a fast system with a quick DMA response time whereas a higher value of THRESH corre- sponds to a sluggish system with slower DMA response time A write to the configuration register is also used to enable implied seeks if that feature is desired Lock This command will lock the FIFO parameters which will leave them unaffected following a reset Set the LOCK bit to 1 to lock the parameters Specify Command After a reset a specify command must always be issued in the initialization sequence This is be- cause there is no default for these values With this com- mand you will set up the motor on and motor off times as well as the step rate times DMA mode is also enabled via this command Mode Command There are several advanced features that can be enabled via the mode command Head settling time for implied seeks open collector drive interface out- puts ISO format pattern low power modes enabling 255 step pulses for higher density media and FIFO burst mode are just some of the features Recalibrate Drive First access to the drive should be to RECALIBRATE to track 0 Following the recalibrate com- mand it is necessary to issue a SENSE INTERRUPT com- mand to determine if the recalibrate was successful If no track 0 was detected an error will be reported This is a common method to determine if a drive is connected SeekReadWriteFormat At this point the initialization is complete and normal disk IO operations would start to occur In normal operations it would not be necessary to re- initialize prior to each access Normal disk IO operations would include writes to CCR register to change data rates recalibrating to track 0 toggling the motor and drive selects through the DOR register seeking to the appropriate track and initializing the DMA controller prior to ReadWriteFor- mat commands Figure 7-2 shows a block diagram representing the initializa- tion sequence for the PC8477B TLF11332 – 25 FIGURE 7-2 PC8477B Initialization 75 PC8477APC8477B DIFFERENCES There are two differences to note between the 8477A and 8477B versions The NSC command result phase returns a 73H in the 8477B and returns a 72H in the 8477A This command is used strictly to distinguish new revisions of the part The second difference pertains to the Motor On Time (MNT) values when the FDC is in Mode 1 The new table is listed in Table 4-15 of this document The MNT values at 500 kbs for Mode 1 were changed to be the same as the 1 Mbs values The changes to the MNT values should not affect application software 76 REVISION HISTORY Nov 1990 Preliminary PC8477 datasheet May 1992 Preliminary PC8477B datasheet Add new part markings Add PQFP package option Add 125 Mbs data rate support Add Dynamic Window Margin spec Improve ICC and AC databus timings Add applications reference section June 1993 Final PC8477B datasheet Elimination of 125 Mbs data rate support Elimination of FM mode functional testing ESD tolerance spec raised to 2000V Replace tQK spec with tKR and tRK Change tRC spec from 160 ns to 300 ns Change tWDW 300 Kbs from 416 ns to 375 ns 51 |
Similar Part No. - PC8477BV-1 |
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Similar Description - PC8477BV-1 |
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