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PC8477BV-1 Datasheet(PDF) 43 Page - National Semiconductor (TI) |
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PC8477BV-1 Datasheet(HTML) 43 Page - National Semiconductor (TI) |
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43 / 54 page  60 Device Description (Continued) 625 DMA Timing Symbol Parameter Min Max Units tQP DRQ Period (Except Non-Burst DMA) (Note 8) 8 x tDRP m s tQQ DRQ Inactive Non-Burst Pulse Width 300 400 ns tKQ DACK Active Edge to DRQ Inactive 65 ns tRQ RD WR Active Edge to DRQ Inactive (Note 7) 65 ns tQR DRQ to RD WR Active 15 ns tTT TC Active Pulse Width 50 ns tTQ TC Active Edge to DRQ Inactive (Note 9) 75 ns tKK DACK Active Pulse Width 65 ns tKI DACK Inactive Pulse Width 25 ns tKR DACK Setup to RD WR Active 5 ns tRK DACK Hold from RD WR Inactive 0 ns tQW DRQ to End of RD WR (Note 8) (8 x tDRP m s (DRQ Service Time) b 16xtICP) tQT DRQ to TC Active (Note 8) (8 x tDRP m s (DRQ Service Time) b 16xtICP) Note 7 The active edge of RD or WR is recognized only when DACK is active Note 8 Values shown are with the FIFO disabled or with FIFO enabled and THRESH e 0 For nonzero values of THRESH add (THRESHx8xtDRP) to the values shown Note 9 During normal DMA operation TC should occur when DACK is active during the last byte of the last sector transferred TLF11332 – 19 FIGURE 6-4 DMA Timing 43 |
Similar Part No. - PC8477BV-1 |
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Similar Description - PC8477BV-1 |
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