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PC8477BV-1 Datasheet(PDF) 32 Page - National Semiconductor (TI) |
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PC8477BV-1 Datasheet(HTML) 32 Page - National Semiconductor (TI) |
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32 / 54 page  50 Functional Description (Continued) DACK asserted by itself without a RD or WR strobe is also counted as a transfer If RD or WR are not being strobed for each byte then DACK must be strobed for each byte so that the floppy controller can count the number of bytes correct- ly A new command the Verify command has been added to allow easier verification of data written to the disk without the need of actually transferring the data on the data bus 5323 Interrupt ModeFIFO Disabled If the Interrupt (Non-DMA) mode is selected INT is asserted instead of DRQ when each byte is ready to be transferred The Main Status Register should be read to verify that the interrupt is for a data transfer The RQM and NON DMA bits (D7 and D5) in the MSR will be set The interrupt will be cleared when the byte is transferred to or from the Data Register CS and RD or CS and WR must be used to trans- fer the data in or out of the Data Register (A2 – A0 must be valid) CS asserted by itself is not significant CS must be asserted with RD or WR for a read or write transfer to be recognized The mP should transfer the byte within the data transfer service time (see Section 37) If the byte is not transferred within the time allotted an Overrun Error will be indicated in the Result Phase when the command terminates at the end of the current sector An interrupt will also be generated after the last byte is transferred This indicates the beginning of the Result Phase The RQM and DIO bits (D7 and D6) in the MSR will be set and the NON DMA bit (D5) will be cleared This interrupt is cleared by reading the first result byte 5324 Interrupt ModeFIFO Enabled The Interrupt (Non-DMA) mode with the FIFO enabled is very similar to the Non-DMA mode with the FIFO disabled In this case INT is asserted instead of DRQ under the exact same FIFO threshold trigger conditions The MSR should be read to verify that the interrupt is for a data transfer The RQM and NON DMA bits (D7 and D5) in the MSR will be set CS and RD or CS and WR must be used to transfer the data in or out of the Data Register (A2 – A0 must be valid) CS asserted by itself is not significant CS must be asserted with RD or WR for a read or write transfer to be recognized The Burst mode may be used to hold the INT pin active during a burst or the Non-Burst mode may be used to tog- gle the INT pin for each byte of a burst The Main Status Register is always valid from the mP point of view For ex- ample during a read command after the last byte of data has been read from the disk and placed in the FIFO the MSR will still indicate that the Execution Phase is active and that data needs to be read from the Data Register Only after the last byte of data has been read by the mP from the FIFO will the Result Phase begin The same overrun and underrun error procedures from the DMA mode apply to the Non-DMA mode Also whether there is an error or not an interrupt is generated at the end of the Execution Phase and is cleared by reading the first Result Phase byte 5325 Software Polling If the Non-DMA Mode is selected and interrupts are not suitable the mP can poll the MSR during the Execution Phase to determine when a byte is ready to be transferred The RQM bit (D7) in the MSR reflects the state of the INT signal Otherwise the data transfer is similar to the Interrupt Mode described above This is true for the FIFO enabled or disabled 533 Result Phase During the Result Phase the mP reads a series of bytes from the data register These bytes indicate the status of the command This status may indicate whether the command executed properly or contain some control information (see the Command Description Table and Status Register De- scription) These Result Phase bytes are read in the order specified for that particular command Some commands will not have a result phase Also the number of result bytes varies with each command All of the result bytes must be read from the Data Register before the next command can be issued Like the Command Phase the Main Status Register con- trols the flow of result bytes and must be polled by the software before reading each Result Phase byte from the Data Register The RQM bit (D7) and DIO bit (D6) must both be set before each result byte can be read After the last result byte is read the COM PROG bit (D4) in the MSR will be cleared and the controller will be ready for the next com- mand 534 Idle Phase After a hardware or software reset or after the chip has recovered from the power down mode the controller enters the Idle Phase Also when there are no commands in prog- ress the controller will be in the Idle Phase The controller will be waiting for a command byte to be written to the Data Register The RQM bit will be set and the DIO bit will be cleared in the MSR After receiving the first command (op- code) byte the controller will enter the Command Phase When the command is completed the controller again en- ters the Idle Phase The Data Separator will remain synchro- nized to the reference frequency while the controller is idle While in the Idle Phase the controller will periodically enter the Drive Polling Phase (see below) 535 Drive Polling Phase While in the Idle Phase the controller will enter a Drive Poll- ing Phase every 1 ms (based on the 500 kbs data rate) While in the Drive Polling Phase the controller will interro- gate the Ready Changed status for each of the four logical drives The internal Ready line for each drive is toggled only after a hardware or software reset and an interrupt will be generated for drive 0 At this point the software must issue four Sense Interrupt commands to clear the Ready Changed State status for each drive This requirement can be eliminated if drive polling is disabled via the POLL bit in the Configure command The Configure command must be issued within 500 ms of the hardware or software reset for drive polling to be disabled Even if drive polling is disabled drive stepping and delayed power down will occur in the Drive Polling Phase The con- troller will check the status of each drive and if necessary it will issue a step pulse on the STEP output with the DIR signal at the appropriate logic level Also the controller uses the Drive Polling Phase to control the Automatic Low Power mode When the Motor Off time has expired the controller will wait 512 ms (based on 500 kbs or 1 Mbs data rate) before powering down if this function is enabled via the Mode command 32 |
Similar Part No. - PC8477BV-1 |
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Similar Description - PC8477BV-1 |
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