 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PC8477BV-1 Datasheet(PDF) 30 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC8477BV-1 Datasheet(HTML) 30 Page - National Semiconductor (TI) |
|
|
30 / 54 page  40 Command Set Description (Continued) If MT was set in the Opcode command byte and the last sector of side 0 has been transferred the controller will then continue with side 1 starting with sector 1 and continuing until EOT Sector is reached or TC occurs Result phase terminattion values listed in Table 4-7 4224 Write Deleted Data The Write Deleted Data command receives data from the host and writes logical sectors containing a Deleted Data AM to the selected drive This command is identical to the Write Data command except that a Deleted Data AM is writ- ten to the Data Field instead of a Normal Data AM 50 Functional Description The PC8477B is pin compatible with the 82077AA floppy disk controller It is software compatible with the DP8473 and 82077AA floppy disk controllers Upon a power-on re- set the 16 byte FIFO will be disabled Also the disk inter- face outputs will be configured as active push-pull outputs which are compatible with both CMOS inputs and open-col- lector resistor terminated disk drive inputs The FIFO can be enabled with the Configure command The FIFO can be very useful at the higher data rates with systems that have a large amount of DMA bus latency or with multi-tasking systems such as the EISA or MCA bus structures The PC8477B will support all the DP8473 Mode command features as well as some additional features These include control over the enabling of the FIFO for reads and writes a Non-Burst mode for the FIFO a bit that will configure the disk interface outputs as open-drain outputs and pro- grammability of the DENSEL output 51 MICROPROCESSOR INTERFACE The PC8477B interface to the microprocessor consists of the CS RD and WR lines which access the chip for reads and writes the data lines D7 – D0 the address lines A2 – A0 which select the register to be accessed (see Table 3-1) the INT signal and the DMA interface signals DRQ DACK and TC It is through this microprocessor interface that the floppy controller receives commands transfers data and returns status information 52 MODES OF OPERATION The PC8477B has three modes of operation PC-AT mode PS2 mode and Model 30 mode which are determined by the state of the IDENT pin and MFM pin IDENT can be tied directly to VCC or GND The MFM pin must be tied high or low with a 10 kX resistor (there is an internal 40 kX –50 kX resistor on the MFM pin) The state of these pins is interro- gated by the controller during a chip reset to determine the mode of operation See Section 30 Register Description for more details on the register set used for each mode of oper- ation After chip reset the state of IDENT can be changed to change the polarity of DENSEL (see Section 20 Pin De- scription) PC-AT Mode (IDENT tied high MFM is a don’t care) The PC-AT register set is enabled The DMA enable bit in the Digital Output Register becomes valid (INT and DRQ can be TRI-STATE) TC and DENSEL become active high signals (defaults to a 525 floppy drive) PS2 Mode (IDENT tied low MFM pulled high internally) This mode supports the PS2 Models 506080 configura- tion and register set The DMA enable bit in the Digital Out- put Register becomes a don’t care (INT and DRQ signals will always be valid) TC and DENSEL become active low signals (default to 35 floppy drive) Model 30 Mode (IDENT tied low MFM pulled low exter- nally) This mode supports the PS2 Model 30 configuration and register set The DMA enable bit in the Digital Output Register becomes valid (INT and DRQ can be TRI-STATE) TC is active high and DENSEL becomes active low (default to 35 floppy drive) 53 CONTROLLER PHASES The PC8477B has three separate phases of a command the Command Phase the Execution Phase and the Result Phase Each of these controller phases will determine how data is transferred between the floppy controller and the host microprocessor In addition when no command is in progress the controller is in the Idle Phase or Drive Polling Phase 531 Command Phase During the Command Phase the mP writes a series of bytes to the Data Register The first command byte contains the opcode for the command and the controller will know how many more bytes to expect based on this opcode byte The remaining command bytes contain the particular parameters required for the command The number of command bytes will vary for each particular command All the command bytes must be written in the order specified in the Command Description Table The Execution Phase starts immediately after the last byte in the Command Phase is written Prior to performing the Command Phase the Digital Output Register should be set and the data rate should be set with the Data Rate Select Register or Configuration Control Register The Main Status Register controls the flow of command bytes and must be polled by the software before writing each Command Phase byte to the Data Register Prior to writing a command byte the RQM bit (D7) must be set and the DIO bit (D6) must be cleared in the MSR After the first command byte is written to the Data Register the CMD PROG bit (D4) will also be set and will remain set until the last Result Phase byte is read If there is no Result Phase the CMD PROG bit will be cleared after the last command byte is written A new command may be initiated after reading all the result bytes from the previous command If the next command requires selecting a different drive or changing the data rate the DOR and DSR or CCR should be updated If the com- mand is the last command then the software should de- select the drive Note As a general rule the operation of the controller core is independent of how the mP updates the DOR DSR and CCR The software must ensure that the manipulation of these registers is coordinated with the controller operation 532 Execution Phase During the Execution Phase the disk controller performs the desired command Commands that involve data trans- fers such as a read write or format operation will require the mP to write or read data to or from the Data Register at this time Some commands such as a Seek or Recalibrate will control the readwrite head movement on the disk drive during the Execution Phase via the disk interface signals The execution of other commands does not involve any ac- tion by the mP or disk drive and consists of an internal operation by the controller If there is data to be transferred between the mP and the controller during the Execution there are three methods that can be used DMA mode interrupt transfer mode and 30 |
Similar Part No. - PC8477BV-1 |
|
Similar Description - PC8477BV-1 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
