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TPS22810

SLVSDH0B – DECEMBER 2016 – REVISED MAY 2017

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Copyright © 2016–2017, Texas Instruments Incorporated

Feature Description (continued)

•

QOD pin is unused and left floating. Using this method, there is no quick output discharge functionality, and

the output remains floating after the switch is disabled.

Note that during thermal shutdown, the QOD functionality is not available. The device does not discharge the

load as RPD does not become engaged.

-t/τ

where

•

•

t is the time since power supply removal (s)

•

(2)

resistance. See Table 1 for QOD fall times.

(1)

TYPICAL VALUES WITH QOD SHORTED TO VOUT

Table 1. QOD Fall Times

(1)

18

470

4700

47000

470

4700

47000

12

450

4500

45000

450

4500

45000

9

440

4400

44000

440

4400

44000

5

500

5000

50000

480

4800

48000

3.3

600

6000

60000

570

5700

57000

9.3.2.1 QOD when System Power is Removed

The adjustable QOD can be used to control the power down sequencing of a system even when the system

UVLO level, the pull-down resistance RPD becomes disabled and the output no longer becomes discharged. If

there is still remaining charge on the output capacitor, this results in longer fall times. Care must be taken such

9.3.2.2 Internal QOD Considerations

not be driven.

9.3.3 EN/UVLO

As an input pin, EN/UVLO controls the ON and OFF state of the internal MOSFET. In its high state, the internal

MOSFET is enabled. A low on this pin turns off the internal MOSFET. High and Low levels are specified in the

parametric table of the datasheet

A voltage V(EN/UVLO < V(ENF) on this pin turns off the internal FET, thus disconnecting VIN from VOUT, while

voltage below V(SHUTF) takes the device into shutdown mode, with IQ less than 1 μA to ensure minimal power

loss.