J(MAX)

A

D(MAX)

JA

T

T

P

-

=

q

1

VOUT

2

QOD

3

CT 4

EN/UVLO

5

GND

6

VIN

VIA to Power Ground Plane

24

TPS22810

SLVSDH0B – DECEMBER 2016 – REVISED MAY 2017

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Copyright © 2016–2017, Texas Instruments Incorporated

12 Layout

12.1 Layout Guidelines

1. VIN and VOUT traces must be as short and wide as possible to accommodate for high current.

2. The VIN pin must be bypassed to ground with low ESR ceramic bypass capacitors. The typical

recommended bypass capacitance is 1-μF ceramic with X5R or X7R dielectric. This capacitor must be

placed as close to the device pins as possible.

12.2 Layout Example

Figure 34. Recommended Board Layout

12.3 Thermal Considerations

For best performance, all traces must be as short as possible. To be most effective, the input and output

capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have

on normal and short-circuit operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic

electrical effects along with minimizing the case to ambient thermal impedance.

The maximum IC junction temperature must be restricted to 150°C under normal operating conditions. To

Equation 14.

where

•

•

•

•

dependent upon board layout.

(14)