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TPS22810 Datasheet(PDF) 18 Page - Texas Instruments |
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TPS22810 Datasheet(HTML) 18 Page - Texas Instruments |
18 / 35 page ![]() Power Supply EN/ UVLO GND VIN CT VOUT OFF ON TPS22810 QOD Copyright © 2016, Texas Instruments Incorporated CL RL CIN 18 TPS22810 SLVSDH0B – DECEMBER 2016 – REVISED MAY 2017 www.ti.com Product Folder Links: TPS22810 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 10 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.1 Application Information This section highlights some of the design considerations when implementing this device in various applications. A PSPICE model for this device is also available in the product page of this device on www.ti.com (See the Device Support section for more information). 10.1.1 ON and OFF Control The EN/UVLO pin controls the state of the switch. Asserting EN/UVLO high enables the switch. EN/UVLO is active high and has a low threshold, making it capable of interfacing with low-voltage signals. The EN/UVLO pin is compatible with standard GPIO logic thresholds. It can be used with any microcontroller with 1.2 V or higher GPIO voltage. This pin cannot be left floating and must be driven either high or low for proper functionality. 10.1.2 Input Capacitor (Optional) To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a discharged load capacitor, a capacitor needs to be placed between VIN and GND. A 1-μF ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop during high current applications. When switching heavy loads, it is recommended to have an input capacitor about 10 times higher than the output capacitor to avoid excessive voltage drop. 10.1.3 Output Capacitor (Optional) Due to the integrated body diode in the NMOS switch, a CIN greater than CL is highly recommended. A CL greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This can result in current flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN dip caused by inrush currents during startup; however, a 10 to 1 ratio for capacitance is not required for proper functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) can cause slightly more VIN dip upon turnon due to inrush currents. This can be mitigated by increasing the capacitance on the CT pin for a longer rise time. 10.2 Typical Application This typical application demonstrates how the TPS22810 can be used to power downstream modules. Figure 21. Typical Application Schematic |
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Similar Description - TPS22810_17 |
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