VIN

VOUT

VIN

EN/

UVLO

GND

GATE

CONTROL

Thermal

Shutdown

2.54 V

2.4 V

1.23 V

1.13 V

Copyright © 2016, Texas Instruments Incorporated

VIN

VOUT

VIN

EN/

UVLO

GND

GATE

CONTROL

Thermal

Shutdown

2.54 V

2.4 V

1.23 V

1.13 V

GPIO

Copyright © 2016, Texas Instruments Incorporated

16

TPS22810

SLVSDH0B – DECEMBER 2016 – REVISED MAY 2017

www.ti.com

Product Folder Links: TPS22810

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Copyright © 2016–2017, Texas Instruments Incorporated

Figure 19. Using 1.8 V/3.3 V GPIO Signal Directly from Processor

Figure 20. Default UVLO Threshold V(UVR) Using No Additional External Components

9.3.4 Adjustable Rise Time (CT)

A capacitor to GND on the CT pin sets the slew rate. The voltage on the CT pin can be as high as 2.5 V. An

approximate formula for the relationship between CT and slew rate is shown in Equation 3. This equation

accounts for 10% to 90% measurement on VOUT and does NOT apply for CT < 1 nF.

Use Table 2 to determine rise times for when Ct

≥ 1 nF.

SR = 46.62 / Ct

where

•

SR is the slew rate (in V/µs)