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ML9059E Datasheet(PDF) 58 Page - LAPIS Semiconductor Co., Ltd. |
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ML9059E Datasheet(HTML) 58 Page - LAPIS Semiconductor Co., Ltd. |
58 / 72 page FEDL9059E-01 LAPIS Semiconductor ML9059E 58/72 MPU INTERFACE The ML9059E series ICs can be connected directly to the 80-series and 68-series MPUs. Further, by using the serial interface, it is possible to operate the LSI with a minimum number of signal lines. In addition, it is possible to expand the display area by using the ML9059E series LSIs in a multiple chip configuration. In this case, it is possible to select the individual LSI to be accessed using the chip select signals. 80-Series MPU 68-Series MPU Serial interface V DD RESET V SS V CC GND A0 A1 to A7 IORQ DB0 to DB7 RD WR RES V DD V SS A0 CS1 CS2 DB0 to DB7 RD WR RES C86 P/S Decoder V DD RESET V SS V CC GND A0 A1 to A15 VMA DB0 to DB7 E R/W RES V DD V SS A0 CS1 CS2 DB0 to DB7 E R/W RES C86 P/S Decoder V DD RESET V SS V CC GND Port 5 Port1 Port2 RES V DD V SS A0 CS1 CS2 SI SCL RES C86 P/S Can be tied to either level. Port 4 Port 3 |
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