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ML9059E Datasheet(PDF) 54 Page - LAPIS Semiconductor Co., Ltd. |
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ML9059E Datasheet(HTML) 54 Page - LAPIS Semiconductor Co., Ltd. |
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54 / 72 page  FEDL9059E-01 LAPIS Semiconductor ML9059E 54/72 EXAMPLES OF SETTINGS FOR THE INSTRUCTIONS When Using the Internal Power Supply Immediately After Power-on *(a): Carry out power control set within 5ms after releasing the reset state. The 5ms duration changes depending on the panel characteristics and the value of the smoothing capacitor. We recommend verification of operation using an actual unit. *(b): When trace resistance in COG mounting does not exist, wait for over 300 ms. Since this value varies with trace resistance, V1, smoothing capacitors, or voltage multiplier capacitors in COG mounting, confirm operation on an actual circuit board when using this LSI. Notes: Sections to be referred to *1: Functional description “Reset circuit” *2: Description of operation “LCD bias set” *3: Description of operation “ADC select” *4: Description of operation “Common output state select” *5: Description of operation “Line reversal/frame reversal drive select” *6: Functional description “Power supply circuit”, Operation description “Voltage V1 adjustment internal resistor ratio set” *7: Functional description “Power supply circuit”, Description of operation “Electronic potentiometer” *8: Functional description “Power supply circuit”, Description of operation “Power control set” VDD-VSS Power supply ON when the pin RES = “L” Power supply stabilization Release reset state ( RES Pin = “H”) Initial settings state (default) *1 Wait for more than 300 ms Function setting using command input (user settings) LCD bias set ADC select Common output state select Line reversal/frame reversal drive select *2 *3 *4 *5 Function setting using command input (user settings) Setting voltage V1 adjustment internal resistor ratio Electronic potentiometer *6 *7 *8 *(a) Function stabilization using command input (user settings) Power control set Initial setting state complete *(b) |
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