ML9058E datasheet(26/76 Pages) LAPIS

Part #	ML9058E

Description	132-Channel LCD Driver

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Manufacturer	LAPIS [LAPIS Semiconductor Co., Ltd.]

Direct Link	http://www.lapis-semi.com/

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26 / 76 page

FEDL9058E-01

LAPIS Semiconductor

ML9058E

26/76

Display Timing Generator Circuit

This circuit generates the timing signals for the line address circuit and the display data latch circuit from the

display clock. The display data is latched in the display data latch circuit and is output to the segment drive output

pins in synchronization with the display clock. This circuit generates the timing signals for the line address circuit

and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit

and is output to the segment drive output pins in synchronization with the display clock. The read out of the

display data to the LCD drive circuits is completely independent of the display data RAM access from the MPU.

As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed

asynchronously during the LCD display. Also, the internal common timing and LCD frame reversal (FR) signals

are generated by this circuit from the display clock. The drive waveforms of the frame reversal drive method

shown in Fig. 5(a) for the LCD drive circuits are generated by this circuit. The drive waveforms of the line reversal

drive method shown in Fig. 5(b) are also generated by the command.

RAM

DATA

VSS

V5

COM1

48 49

1

2

3

4

5

6

V2

V1

VSS

V4

SEGn

V3

V1

44 45 46 47 48 49 1

23

4

5

6

VSS

V5

COM0

V2

V1

FR

LCDCK

(display clock)

Fig. 5(a) Waveforms in the frame reversal drive method

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ML9058E Datasheet(PDF) 26 Page - LAPIS Semiconductor Co., Ltd.

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