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ML9058E Datasheet(PDF) 23 Page - LAPIS Semiconductor Co., Ltd. |
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ML9058E Datasheet(HTML) 23 Page - LAPIS Semiconductor Co., Ltd. |
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23 / 76 page  FEDL9058E-01 LAPIS Semiconductor ML9058E 23/76 Display Data RAM Display data RAM This is the RAM storing the dot data for display and has an organization of 65 (8 pages 8 bits +1) 132 bits. It is possible to access any required bit by specifying the page address and the column address. Since the display data DB7 to DB0 from the MPU corresponds to the LCD display in the direction of the common lines as shown in Fig. 3, there are fewer restrictions during display data transfer when the ML9058E is used in a multiple chip configuration, thereby making it easily possible to realize a display with a high degree of freedom. Also, since the display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the signal read operation for the LCD drive. Consequently, the display is not affected by flickering, etc., even when the display data RAM is accessed asynchronously during the LCD display operation. DB0 0 1 1 1 0 COM0 DB1 1 0 0 0 0 COM1 DB2 0 0 0 0 0 COM2 DB3 0 1 1 1 0 COM3 DB4 1 0 0 0 0 COM4 Display data RAM LCD Display Fig. 3 Relationship between display data RAM and LCD display Page address circuit The page address of the display data RAM is specified using the page address set command as shown in Fig. 4. Specify the page address again when accessing after changing the page. The page address 8 (DB3, DB2, DB1, DB0 1, 0, 0, 0) is the RAM area dedicated to the indicator, and only the display data DB0 is valid in this page. Column address circuit The column address of the display data RAM is specified using the column address set command as shown in Fig. 4. Since the specified column address is incremented (by +1) every time a display data read/write command is issued, the MPU can access the display data continuously. Further, the incrementing of the column address is stopped at the column address of 83(H). Since the column address and the page address are independent of each other, it is necessary, for example, to specify separately the new page address and the new column address when changing from column 83(H) of page 0 to column 00(H) of page 1. Also, as is shown in Table 5, it is possible to reverse the correspondence relationship between the display data RAM column address and the segment output using the ADC command (the segment driver direction select command). This reduces the IC placement restrictions at the time of assembling LCD modules. Table 5 Correspondence relationship between the display data RAM column address and the segment output SEGMENT Output ADC SEG0 SEG131 DB0 = “0” 0(H) Column Address 83(H) DB0 = “1” 83(H) Column Address 0(H) |
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