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ML9058E Datasheet(PDF) 21 Page - LAPIS Semiconductor Co., Ltd. |
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ML9058E Datasheet(HTML) 21 Page - LAPIS Semiconductor Co., Ltd. |
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21 / 76 page  FEDL9058E-01 LAPIS Semiconductor ML9058E 21/76 Serial Interface When the serial interface is selected (P/S = “L”), the serial data input (SI) and the serial clock input (SCL) can be accepted if the chip is in the active state (CS1 = “L” and CS2 = “H”). The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data is read in from the serial data input pin in the sequence DB7, DB6, ... , DB0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial clock pulse and processed further. The identification of whether the serial data is display data or command is judged based on the A0 input, and the data is treated as display data when A0 is “H” and as command when A0 is “L”. The A0 input is read in and identified at the rising edge of the (8 n) th serial clock pulse after the chip has become active. Fig. 1 shows the signal chart of the serial interface. (When the chip is not active, the shift register and the counter are reset to their initial states. No data read out is possible in the case of the serial interface. It is necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL signal. We recommend verification of operation in an actual unit.) Fig. 1 Signal chart during serial interface Chip select The ML9058E has the two chip select pins CS1and CS2, and the MPU interface or the serial interface is enabled only when CS1 = “L” and CS2 = “H”. When the chip select signals are in the inactive state, the DB0 to DB7 lines will be in the high impedance state and the inputs A0, RD, and WR will not be effective. When the serial interface has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state. Accessing the display data RAM and the internal registers Accessing the ML9058E from the MPU side requires merely that the cycle time (tCYC) be satisfied, and high speed data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the ML9058E carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data bus. For example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus holder, and is then written into the display data RAM before the next data read cycle. Further, when the MPU reads out data in the display data RAM, first a dummy data read cycle is carried out to temporarily store the data in the bus holder which is then placed on the system bus and is read out during the next read cycle. There is a restriction on the read sequence of the display data RAM, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading. Therefore, always one dummy read is necessary immediately after setting the address or after a write cycle: (The status read cannot use dummy read cycles.) This relationship is shown in Figs 2(a) and 2(b). DB7 SI SCL A0 CS2 CS1 1 DB6 2 DB5 3 DB4 4 DB3 5 DB2 6 DB1 7 DB0 8 DB7 9 DB6 10 DB5 11 DB4 12 DB3 13 DB2 14 |
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