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ML9058E Datasheet(PDF) 17 Page - LAPIS Semiconductor Co., Ltd. |
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ML9058E Datasheet(HTML) 17 Page - LAPIS Semiconductor Co., Ltd. |
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17 / 76 page  FEDL9058E-01 LAPIS Semiconductor ML9058E 17/76 Function Pin name Number of pins I/O Description This is the clock input/output pin. The function of this pin will be as follows depending on the states of M/ S and CLS signals. M/ S CLS CL “H” Output “H” “L” Input “H” Input “L” “L” Input CL 1 I/O When the ML9058E is used in the master/slave mode, the corresponding CL pin has to be connected. FR 1 I/O This is the input/output pin for LCD display frame reversal signal. M/ S = “H”: Output M/ S = “L”: Input When the ML9058E is used in the master/slave mode, the corresponding FR pin has to be connected. DOF 1 I/O This is the blanking control pin for the LCD display. M/ S = “H”: Output M/ S = “L”: Input When the ML9058E is used in the master/slave mode, the corresponding DOF pin has to be connected. Display timing generator circuit FRS 1 O This is the output pin for static drive. This pin is used in combination with the FR pin. IRS 1 I This is the pin for selecting the resistor for adjusting the voltage V1. IRS = “H”: The internal resistor is used. IRS = “L”: The internal resistor is not used. The voltage V1 is adjusted using the external potential divider resistors connected to the pins VR. This pin is effective only in the master operation. This pin is tied to the “H” or the “L” level during slave operation. VDD 12 — These pins are tied to the MPU power supply pin VCC. VSS 12 — These are the 0 V pins connected to the system ground (GND). Power supply circuit VIN 5 — These are the reference power supply pins of the voltage multiplier circuit for driving the LCD. |
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