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ML9058E Datasheet(PDF) 11 Page - LAPIS Semiconductor Co., Ltd. |
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ML9058E Datasheet(HTML) 11 Page - LAPIS Semiconductor Co., Ltd. |
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11 / 76 page  FEDL9058E-01 LAPIS Semiconductor ML9058E 11/76 [VDD = 4.5 to 5.5 V, Tj = –40 to +85°C] Rated value Parameter Symbol Condition Min Max Unit Address hold time tAH6 5 — Address setup time tAW6 5 — System cycle time tCYC6 166 — Data setup time tDS6 30 — Data hold time tDH6 10 — Access time tACC6 CL = 100 pF — 70 Output disable time tOH6 10 50 Read tEWHR 70 — Enable H pulse width Write tEWHW 30 — Read tEWLR 60 — Enable L pulse width Write tEWLW 60 — ns [VDD = 3.7 to 4.5 V, Tj = –40 to +85°C] Rated value Parameter Symbol Condition Min Max Unit Address hold time tAH6 5 — Address setup time tAW6 5 — System cycle time tCYC6 300 — Data setup time tDS6 40 — Data hold time tDH6 15 — Access time tACC6 — 140 Output disable time tOH6 CL = 100 pF 10 100 Read tEWHR 120 — Enable H pulse width Write tEWHW 60 — Read tEWLR 60 — Enable L pulse width Write tEWLW 60 — ns Note 1: The input signal rise and fall times are specified as 15ns or less. When using the system cycle time for fast speed, the specified values are (tr + tf) (t CYC6 – tEWLW – tEWHW) or (tr + tf) (tCYC6 – tEWLR – tEWHR). Note 2: All timings are specified taking the levels of 20% and 80% of VDD as the reference. Note 3: The values of tEWLW and tEWLR are specified during the overlapping period of CS1 at “L” (CS2 = “H”) and the “H” level of E. |
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