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SAA7824 Datasheet(PDF) 38 Page - NXP Semiconductors |
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SAA7824 Datasheet(HTML) 38 Page - NXP Semiconductors |
38 / 89 page 2003 Oct 01 38 Philips Semiconductors Product specification CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control SAA7824 7.17.1 MICROCONTROLLER INTERFACE (4-WIRE BUS MODE) 7.17.1.1 Writing data to registers 0 to F The sixteen 4-bit programmable configuration registers, 0 to F (see Table 15), can be written to via the microcontroller interface using the protocol shown in Fig.25. It should be noted that SILD must be held HIGH; A3 to A0 identifies the register number and D3 to D0 is the data. The data is latched into the register on the LOW-to-HIGH transition of RAB. 7.17.1.2 Writing repeated data to registers 0 to F The same data can be repeated several times (e.g. for a fade function) by applying extra RAB pulses as shown in Fig.26. It should be noted that SCL must stay HIGH between RAB pulses. 7.17.1.3 Multiple writes to the new shadow registers Some of the new shadow registers are a multiple of four bits in length and require a number of write operations to fill them up; see Section 7.17.5. They must be completely filled before writing to another register, otherwise unpredictable behaviour may result. The protocol for writing to these registers is exactly the same as the decoder registers; see Fig.25. The write command must be executed multiple times with the same address content. The first four bits of data in a sequence of write commands represent the most significant nibble of the register, while the last four represent the least significant nibble. The data content can change from one write to the next without consequence. 7.17.1.4 Reading decoder status information on SDA There are several internal status signals, selected via register 2, which can be made available on the SDA line: • SUBQREADY-I: LOW if new subcode word is ready in Q-channel register • MOTSTART1: HIGH if motor is turning at 75% or more of nominal speed • MOTSTART2: HIGH if motor is turning at 50% or more of nominal speed • MOTSTOP: HIGH if motor is turning at 12% or less of nominal speed; can be set to indicate 6% or less (instead of 12% or less) via register E • PLL lock: HIGH if sync coincidence signals are found • V1: follows input on pin V1 • V2: follows input on pin V2 • MOTOR-OV: HIGH if the motor servo output stage saturates. The status read protocol is illustrated in Fig.27. It should be noted that SILD must be held HIGH. 7.17.1.5 Reading Q-channel subcode To read the Q-channel subcode direct in the 4-wire bus mode, the SUBQREADY-I signal should be selected as the status signal. The subcode read protocol is illustrated in Fig.28. It should be noted that SILD must be held HIGH; after subcode read starts, the microcontroller may take as long as it wants to terminate the read operation. When enough subcode has been read (1 to 96 bits), the reading can be terminated by pulling RAB LOW. Alternatively, the Q-channel subcode can be read using a servo command as follows: • Use the read high-level status command to monitor the subcode ready signal • Send the read subcode command and read the required number of bytes (up to 12) • Send the read high-level status command; to re-enable the decoder interface. 7.17.1.6 Behaviour of the SUBQREADY-I signal When the CRC of the Q-channel word is good, and no subcode is being read, the SUBQREADY-I status signal will react as illustrated in Fig.29. When the CRC is good and the subcode is being read, the timing in Fig.30 applies. If t1 (SUBQREADY-I status LOW to end of subcode read) is below 2.6/n ms, then t2 = 13.1/n ms (i.e. the microcontroller can read all subcode frames if it completes the read operation within 2.6/n ms after the subcode is ready). If these criteria are not met, it is only possible to guarantee that t3 will be below 26.2/n ms (approximately). If subcode frames with failed CRCs are present, the t2 and t3 times will be increased by 13.1/n ms for each defective subcode frame. It should be noted that in the lock-to-disc mode ‘n’ is replaced by ‘d’, which is the disc speed factor. |
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