SAA7824 datasheet(76/89 Pages) PHILIPS

Part #	SAA7824

Description	CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control (PhonIC)

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Manufacturer	PHILIPS [NXP Semiconductors]

Direct Link	http://www.nxp.com

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76 / 89 page

2003 Oct 01

76

Philips Semiconductors

Product speciﬁcation

CD audio decoder, digital servo and ﬁlterless

DAC with integrated pre-amp and laser control

SAA7824

12 OPERATING CHARACTERISTICS (I2S-BUS TIMING)

VDDD = 1.65 to 1.95 V; VSS =0V; Tamb = 0 to 70 °C; unless otherwise speciﬁed.

Note

1. In the normal operating mode the I2S-bus timing is directly related to the overspeed factor ‘n’. In the lock-to-disc mode

‘n’ is replaced by the disc speed factor ‘d’.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

I2S-bus timing (single speed

× n); see Fig.35; note 1

CLOCK OUTPUT: PIN SCLK (CL = 20 pF)

Tcy

output clock period

sample rate = fs

−

472.4/n

−

ns

sample rate = 2fs

−

236.2/n

−

ns

sample rate = 4fs

−

118.1/n

−

ns

tCH

clock HIGH time

sample rate = fs

166/n

−−

ns

sample rate = 2fs

83/n

−−

ns

sample rate = 4fs

42/n

−−

ns

tCL

clock LOW time

sample rate = fs

166/n

−−

ns

sample rate = 2fs

83/n

−−

ns

sample rate = 4fs

42/n

−−

ns

OUTPUTS: PINS WCLK, DATA AND EF (CL =20pF)

tsu

set-up time

sample rate = fs

95/n

−−

ns

sample rate = 2fs

48/n

−−

ns

sample rate = 4fs

24/n

−−

ns

th

hold time

sample rate = fs

95/n

−−

ns

sample rate = 2fs

48/n

−−

ns

sample rate = 4fs

24/n

−−

ns

DD

V

– 0.8 V

0.8 V

DD

V

– 0.8 V

0.8 V

t CH

MBG407

t CL

clock period Tcy

SCLK

WCLK

DATA

EF

t h

t su

Fig.35 I2S-bus timing diagram.

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