![]() |
Electronic Components Datasheet Search |
|
LMX2306 Datasheet(PDF) 12 Page - National Semiconductor (TI) |
|
|
|
LMX2306 Datasheet(HTML) 12 Page - National Semiconductor (TI) |
12 / 19 page ![]() 1.0 Functional Description (Continued) TABLE 5. FastLock Decoding FastLock Status F[8] F[9] F[10] N[19] (Note 7) FastLock State FastLock Mode #1 1 0 0 1 (Note 7) No Timeout Counter - 1X Divider FastLock Mode #2 1 0 1 1 Timeout Counter - 1X Divider FastLock Mode #3 1 1 0 1 (Note 7) No Timeout Counter - 1/4X Divider FastLock Mode #4 1 1 1 1 Timeout Counter - 1/4X Divider Note 7: When the GO bit N[19] is set to one, the part is forced into the high gain mode. When the timeout counter is activated, termination of the counter cycle resets the GO bit to 0. If the timeout counter is not activated, N[19] must be reprogrammed to zero in order to remove the high gain state. See below for descriptions of each individual FastLock mode. There are two techniques of switching in and out of FastLock. To program the device into any of the FastLock modes, the GO bit N[19] must be set to one to begin FastLock operation. In the first approach, the timeout counter can be used (FastLock 2 and 4) to stay in FastLock mode for a programmable number of phase detector reference cycles (up to 63) and then reset the GO bit automatically. In the second approach (FastLock 1 and 3) without the timeout counter, the PLL will remain in FastLock mode until the user resets the GO bit via the MICROWIRE serial bus. Once the GO bit is set to zero by the timeout counter or by MICROW- IRE, the PLL will then return to normal operation. This transition does not effect the charge on the loop filter capacitors and is en- acted synchronous with the charge pump output. This creates a nearly seamless transition between FastLock and standard mode. FastLock Mode 1 In this mode, the output level of the FL o is programmed in a low state while the ICPo is in the 4x state. The device remains in this state until a command is received, resetting the N[19] bit to zero. Programming N[19] to zero will return the device to normal operation*., i.e., ICP o = 1x and FLo returned to TRI-STATE. FastLock Mode 2 Identical to mode 1, except the switching of the device out of FastLock is controlled by the Timeout counter. The device will remain in FastLock until the timeout counter has counted down the appropriate number of phase detector cycles, at which time the PLL returns to normal operation*. FastLock Mode 3 This mode is similar to mode 1 in that the output level of the FL o is low and the ICPo is switched to the 4x state. Additionally, the R and N divide ratios are reduced by one fourth during the transient, resulting in a 16x im- proved gain. As in mode 1, the device remains in this state until a MICROWIRE command is received, reset- ting the N[19] bit to zero and returning the device to normal operation*. FastLock Mode 4 Identical to mode 3, except the switching of the device out of FastLock is controlled by the Timeout counter. The device will remain in FastLock until the timeout counter has counted down the appropriate number of phase detector cycles, at which time the PLL returns to normal operation*. *Normal Operation FastLock Normal Operation is defined as the device being in low current mode and standard divider values. DS100127-8 www.national.com 12 |
Similar Part No. - LMX2306 |
|
Similar Description - LMX2306 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |