1.0 Functional Description

The simplified block diagram below shows the 21-bit data register, a 14-bit R Counter, an 18-bit N Counter, and a 18-bit Function

Latch (intermediate latches are not shown). The data stream is shifted (on the rising edge of LE) into the DATA input, MSB first.

The last two bits are the Control Bits. The DATA is transferred into the counters as follows:

Control

DATA Location

C1

C2

0

0

R Counter

1

0

N Counter

0

1

Function Latch

1

1

Initialization

1.1 PROGRAMMABLEREFERENCE DIVIDER

If the Control Bits are [C

The 4 bits R15–R18 are for test modes, and should be set to 0 for normal use. The LD precision bit, R19, is described in the

LOCK DETECT OUTPUT CHARACTERISTICS section. Serial data format is shown below.

1.1.1 14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)

Divide

RRRRR

RRRRRRRRR

Ratio

14

13

12

11

10

987654321

3

00000

000000011

4

00000

000000100

•

•••••

•••••••••

16383

11111

111111111

Notes: Divide ratios less than 3 are prohibited.

Divide ratio: 3 to 16383

R1 to R14: These bits select the divide ratio of the programmable reference divider.

DS100127-4

DS100127-5

Note: R15 to R18 are test modes and should be zero for normal operation.

Data is shifted in MSB first.

www.national.com

7