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SCC2681AC1A44 Datasheet(PDF) 20 Page - NXP Semiconductors |
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SCC2681AC1A44 Datasheet(HTML) 20 Page - NXP Semiconductors |
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20 / 29 page  Philips Semiconductors Product data SCC2681 Dual asynchronous receiver/transmitter (DUART) 2004 Apr 06 20 masked off through the OPCR[3:2] = 00 until the T/C is programmed to the desired operational state. In the counter mode, the C/T counts down the number of pulses loaded into CTUR and CTLR by the CPU. Counting begins upon receipt of a counter command. Upon reaching terminal count (0x0000), the counter ready interrupt bit (ISR[3]) is set. The counter continues counting past the terminal count until stopped by the CPU. If OP3 is programmed to be the output of the C/T, the output remains HIGH until terminal count is reached, at which time it goes LOW. The output returns to the HIGH state and ISR[3] is cleared when the counter is stopped by a stop counter command. The CPU may change the values of CTUR and CTLR at any time, but the new count becomes effective only on the next start counter command. If new values have not been loaded, the previous count values are preserved and used for the next count cycle. In the counter mode, the current value of the upper and lower 8 bits of the counter (CTU, CTL) may be read by the CPU. It is recommended that the counter be stopped when reading to prevent potential problems which may occur if a carry from the lower 8 bits to the upper 8 bits occurs between the times that both halves of the counter are read. However, note that a subsequent start counter command will cause the counter to begin a new count cycle using the values in CTUR and CTLR. Output Port Notes The output ports are controlled from three places: the OPCR register, the OPR register, and the MR registers. The default source of data for the OP[7:0] pins is the OPR register. When the OPR is the source for the OP pins, the pins will drive the complement (inverse) of data in the OPR register. The OPCR register, the MR register, and the Command register control the data source for the OP pins. It is this ‘multi-source’ feature of the OP pins that allows them to give the 485 turn-around RTS, DMA, interrupt and various other internal clock signals. The OPCR controls the source of the data for the output ports OP2 through OP7. The data source for output ports OP0 and OP1 is controlled by the MR and CR registers. When the OPR is the source of the data for the output ports, the data at the ports is inverted from that in the OPR register. The content of the OPR register is controlled by the Set and Reset Output Port Bits ‘Commands’. These commands are actually the addresses at 0xE and 0xF, respectively. When these commands are used, action takes place only at the bit locations where ones exist on the data bus. For example, a one in bit location 5 of the data word used with the ‘Set Output Port Bits’ command will result in OPR[5] being set to one. The OP[5] pin would then drive a logical zero (VSS). Similarly, a one in bit position 5 of the data word associated with the ‘Reset Output Ports Bits’ command would set OPR[5] to zero, and hence, the pin OP[5] will drive to a one (VDD). The use of two register locations to control the OPR relieves the software from the burden of keeping a copy of the OPR settings and thus facilitates a bit type manipulation of the individual bits. This is the same reasoning used in the lower four bits of the command register where the Rx and Tx enabling is controlled. The CTS, RTS, CTS Enable Tx signals CTS (Clear To Send) is usually meant to be a signal to the transmitter meaning that it may transmit data to the receiver. The CTS input is on pin IP0 for TxA and on IP1 for TxB. The CTS signal is active LOW; thus, it is called CTSAN for TxA and CTSBN for TxB. RTS is usually meant to be a signal from the receiver indicating that the receiver is ready to receive data. It is also active LOW and is, thus, called RTSAN for RxA and RTSBN for RxB. RTSAN is on pin op0 and RTSBN is on OP1. A receiver’s RTS output will usually be connected to the CTS input of the associated transmitter. Therefore, one could say that RTS and CTS are different ends of the same wire! MR2(4) is the bit that allows the transmitter to be controlled by the CTS pin (IP0 or IP1). When this bit is set to one AND the CTS input is driven HIGH, the transmitter will stop sending data at the end of the present character being serialized. It is usually the RTS output of the receiver that will be connected to the transmitter’s CTS input. The receiver will set RTS HIGH when the receiver FIFO is full AND the start bit of the fourth character is sensed. Transmission then stops with four valid characters in the receiver. When MR2(4) is set to one, CTSN must be at zero for the transmitter to operate. If MR2(4) is set to zero, the IP pin will have no effect on the operation of the transmitter. MR1(7) is the bit that allows the receiver to control OP0. When OP0 (or OP1) is controlled by the receiver, the meaning of that pin will be RTS. However, a point of confusion arises in that OP0 (or OP1) may also be controlled by the transmitter. When the transmitter is controlling this pin, its meaning is not RTS at all. It is, rather, that the transmitter has finished sending its last data byte. Programming the OP0 or OP1 pin to be controlled by the receiver and the transmitter at the same time is allowed, but would usually be incompatible. RTS is expressed at the OP0 or OP1 pin which is still an output port. Therefore, the state of OP0 or OP1 should be set LOW for the receiver to generate the proper RTS signal. The logic at the output is basically a NAND of the OPR register and the RTS signal as generated by the receiver. When the RTS flow control is selected via the MR(7) bit state of the OPR register is not changed. Terminating the use of “Flow Control” (via the MR registers) will return the OP0 or OP1 pins to the control of the OPR register. Transmitter Disable Note The sequence of instructions enable transmitter — load transmit holding register — disable transmitter will result in nothing being sent if the time between the end of loading the transmit holding register and the disable command is less that 3/16 bit time in the 16x mode or one bit time in the 1x mode. Also, if the transmitter, while in the enabled state and underrun condition, is immediately disabled after a single character is loaded to the transmit holding register, that character will not be sent. In general, when it is desired to disable the transmitter before the last character is sent AND the TxEMT bit is set in the status register (TxEMT is always set if the transmitter has underrun or has just been enabled), be sure the TxRDY bit is active immediately before issuing the transmitter disable instruction. TxRDY sets at the end of the “start bit” time. It is during the start bit that the data in the transmit holding register is transferred to the transmit shift register. Non-standard baud rates are available as shown in Table 5 below, via the BRG Test function. |
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