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SCC2681AC1A44 Datasheet(PDF) 15 Page - NXP Semiconductors |
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SCC2681AC1A44 Datasheet(HTML) 15 Page - NXP Semiconductors |
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15 / 29 page  Philips Semiconductors Product data SCC2681 Dual asynchronous receiver/transmitter (DUART) 2004 Apr 06 15 or transmitted character. Likewise, if a mode is deselected the device will switch out of the mode immediately. An exception to this is switching out of autoecho or remote loopback modes: if the deselection occurs just after the receiver has sampled the stop bit (indicated in autoecho by assertion of RxRDY), and the transmitter is enabled, the transmitter will remain in autoecho mode until the entire stop has been retransmitted. MR2A[5] – Channel A Transmitter Request-to-Send Control CAUTION: When the transmitter controls the OP pin (usually used for the RTSN signal) the meaning of the pin is not RTSN at all! Rather, it signals that the transmitter has finished the transmission (i.e., end of block). Note: Please see Application Note AN10251 for more information on this subject. This bit allows deactivation of the RTSN output by the transmitter. This output is manually asserted and negated by the appropriate commands issued via the SOPR and ROPR registers. MR2[5] set to 1 caused the RTSN to be reset automatically one bit time after the character(s) in the transmit shift register and in the THR (if any) are completely transmitted (including the programmed number of stop bits) if a previously issued transmitter disable is pending. This feature can be used to automatically terminate the transmission as follows: 1. Program the auto-reset mode: MR2[5]=1 2. Enable transmitter, if not already enabled 3. Set OPR[0] or OPR[1] to ‘1’ via the SOPR and ROPR registers 4. Send message 5. After the last character of the message is loaded to the THR, disable the transmitter. (If the transmitter is underrun, a special case exists. See note below.) 6. The last character will be transmitted and the RTSN will be reset one bit time after the last stop bit is sent. NOTE: The transmitter is in an underrun condition when both the TxRDY and the TxEMT bits are set. This condition also exists immediately after the transmitter is enabled from the disabled or reset state. When using the above procedure with the transmitter in the underrun condition, the issuing of the transmitter disable must be delayed from the loading of a single, or last, character until the TxRDY becomes active again after the character is loaded. MR2A[4] – Channel A Clear-to-Send Control If this bit is 0, CTSAN has no effect on the transmitter. If this bit is a 1, the transmitter checks the state of CTSAN (IPO) each time it is ready to send a character. If IPO is asserted (LOW), the character is transmitted. If it is negated (HIGH), the TxDA output remains in the marking state and the transmission is delayed until CTSAN goes LOW. Changes in CTSAN while a character is being transmitted do not affect the transmission of that character.. MR2A[3:0] – Channel A Stop Bit Length Select This field programs the length of the stop bit appended to the transmitted character. Stop bit lengths of .563 TO 1 AND .563 to 2 bits. In increments of 0.625 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1.0625 to 2 stop bits can be programmed in increments of .0625 bit. The receiver only checks for a ‘mark’ condition at the center of the first stop bit position (one bit time after the last data bit, or after the parity bit is enabled) in all cases. If an external 1 × clock is used for the transmitter, MR2A[3] = 0 selects one stop bit and MR2A[3] = 1 selects two stop bits to be transmitted. MR1B – Channel B Mode Register 1 MR1B is accessed when the Channel B MR pointer points to MR1. The pointer is set to MR1 by RESET or by a ‘set pointer’ command applied via CRB. After reading or writing MR1B, the pointer will point to MR2B. MR2B – Channel B Mode Register 2 MR2B is accessed when the Channel B MR pointer points to MR2, which occurs after any access to MR1B. Accesses to MR2B do not change the pointer. The bit definitions for mode registers 1 and 2 are identical to the bit definitions for MRA and MR2A except that all control actions apply to the Channel B receiver and transmitter and the corresponding inputs and outputs. CSRA – Channel A Clock Select Register STandard baud rates are shown below. A read at address 0x2 changes the baud rate generator to give higher speed baud rates. (See Table 5 on page 21.) A subsequent read at address 0x2 changes the baud rate generator back to standard rates. In other words, each read at 0x2 toggles the controlling flip-flop. Table 3. Bit Rate Generator Characteristics Crystal or Clock = 3.6864MHz Normal rate (baud) Actual 16 × clock (kHz) Error (%) 50 0.8 0 75 1.2 0 110 1.759 –0.069 134.5 2.153 0.059 150 2.4 0 200 3.2 0 300 4.8 0 600 9.6 0 1050 16.756 –0.260 1200 19.2 0 1800 28.8 0 2000 32.056 0.175 2400 38.4 0 4800 76.8 0 7200 115.2 0 9600 153.6 0 14.4 k 230.4 0 19.2 k 307.2 0 28.8 k 460.8 0 38.4 k 614.4 0 57.6 k 921.6 0 115.2 k 1843.2 k 0 NOTE: Duty cycle of 16 × clock is 50% ± 1%. Asynchronous UART communications can tolerate frequency error of 4.1% to 6.7% in a “clean” communications channel. The percent of error changes as the character length changes. The above percentages range from 5 bits not parity to 8 bits with parity and one stop bit. The error with 8 bits not parity and one stop bit is 4.6%. If a stop bit length of 9/16 is used, the error tolerance will approach 0 due to a variable error of up to 1/16 bit time in receiver clock phase alignment to the start bit. |
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