Philips Semiconductors

Product data

SCC2681

Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

7

8. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.

9. This parameter is not applicable to the 28-pin device.

10. Operation to 0 MHz is assured by design. However, operation at low frequencies is not tested and has not been characterized.

BLOCK DIAGRAM

8

D0–D7

RDN

WRN

CEN

A0–A3

RESET

INTRN

X1/CLK

X2

4

BUS BUFFER

OPERATION CONTROL

ADDRESS

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR

ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

COUNTER/

TIMER

XTAL OSC

CSRA

CSRB

ACR

CTUR

CHANNEL A

TRANSMIT

HOLDING REG

TRANSMIT

SHIFT REGISTER

RECEIVE

HOLDING REG (3)

RECEIVE

SHIFT REGISTER

MRA1, 2

CRA

SRA

INPUT PORT

CHANGE OF

STATE

DETECTORS (4)

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

TxDA

RxDA

IP0-IP6

OP0-OP7

VCC

GND

CHANNEL B

(AS ABOVE)

IPCR

ACR

OPR

CTLR

RxDB

TxDB

8

7

SD00085

Figure 2. Block Diagram