Philips Semiconductors

Product data

SCC2681

Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

3

PIN CONFIGURATIONS

PIN/FUNCTION

PIN/FUNCTION

1NC

23 NC

2

A0

24 INTRN

3

IP3

25 D6

4A1

26 D4

5

IP1

27 D2

6A2

28 D0

7

A3

29 OP6

8

IP0

30 OP4

9

WRN

31 OP2

10 RDN

32 OP0

11

RXDB

33 TXDA

12 NC

34 NC

13 TXDB

35 RXDA

14 OP1

36 X1/CLK

15 OP3

37 X2

16 OP5

38 RESET

17 OP7

39 CEN

18 D1

40 IP2

19 D3

41 IP6

20 D5

42 IP5

21 D7

43 IP4

22 GND

24

23

22

21

20

19

18

17

16

15

28

27

12

10

11

9

8

7

6

5

4

3

2

1

14

13

26

25

29

30

31

32

33

34

35

36

37

38

39

40

DIP

IP4

IP5

IP6

IP2

CEN

RESET

X2

X1/CLK

RXDA

TXDA

OP0

OP2

OP4

OP6

D0

D2

D4

D6

INTRN

A0

IP3

A1

IP1

A2

A3

IP0

WRN

RDN

RXDB

TXDB

OP1

OP3

OP5

OP7

D1

D3

D5

D7

GND

24

23

22

21

20

19

18

17

16

15

28

27

12

10

11

9

8

7

6

5

4

3

2

1

14

13

26

25

IP2

CEN

RESET

X2

X1/CLK

RXDA

TXDA

OP0

D0

D2

D4

D6

INTRN

GND

D7

D5

D3

D1

OP1

TXDB

RXDB

RDN

WRN

A3

A2

A1

A0

DIP

1

39

17

28

40

29

18

7

PLCC

6

TOP VIEW

INDEX

CORNER

SD00723

Figure 1. Pin configurations

PIN DESCRIPTION

SYMBOL

PIN

TYPE

NAME AND FUNCTION

SYMBOL

PLCC44

DIP40

DIP28

TYPE

NAME AND FUNCTION

D0–D7

28, 18,

27, 19,

26, 20,

25, 21

25, 16,

24, 17,

23, 18,

22, 19

19, 10,

18, 11,

17, 12,

16, 13

I/O

Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status

between the DUART and the CPU. D0 is the least significant bit.

CEN

39

35

26

I

Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU

and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3

inputs. When HIGH, places the D0-D7 lines in the 3-State condition.

WRN

9

8

5

I

Write Strobe: When LOW and CEN is also LOW, the contents of the data bus is

loaded into the addressed register. The transfer occurs on the rising edge of the signal.

RDN

10

9

6

I

Read Strobe: When LOW and CEN is also LOW, causes the contents of the

addressed register to be presented on the data bus. The read cycle begins on the

falling edge of RDN.

A0–A3

2, 4, 6, 7

1, 3, 5,

6

1–4

I

Address Inputs: Select the DUART internal registers and ports for read/write

operations.

RESET

38

34

25

I

Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts

OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channels A and B in the

inactive state, with the TxDA and TxDB outputs in the mark (HIGH) state. Clears Test

modes, sets MR pointer to MR1.

INTRN

24

21

15

O

Interrupt Request: Active-LOW, open-drain, output which signals the CPU that one or

more of the eight maskable interrupting conditions are true.

X1/CLK

36

32

23

I

Crystal 1: Crystal connection or an external clock input. A crystal of a clock the

appropriate frequency (nominally 3.6864 MHz) must be supplied at all times. For crystal

connections see Figure 7, Clock Timing.