 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SCC2681 Datasheet(PDF) 11 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
SCC2681 Datasheet(HTML) 11 Page - NXP Semiconductors |
|
|
11 / 29 page  Philips Semiconductors Product data SCC2681 Dual asynchronous receiver/transmitter (DUART) 2004 Apr 06 11 PROGRAMMING The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. The addressing of the registers is described in Table 1. The contents of certain control registers are initialized to zero on RESET. Care should be exercised if the contents of a register are changed during operation, since certain changes may cause operational problems. For example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. In general, the contents of the MR, the CSR, and the OPCR should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the ACR should only be made while the C/T is stopped. Mode registers 1 and 2 of each channel are accessed via independent auxiliary pointers. The pointer is set to MR1x by RESET or by issuing a ‘reset pointer’ command via the corresponding command register. Any read or write of the mode register while the pointer is at MR1x, switches the pointer to MR2x. The pointer then remains at MR2x, so that subsequent accesses are always to MR2x unless the pointer is reset to MR1x as described above. Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control. Refer to Table 2 for register bit descriptions. Table 1. SCC2681 Register Addressing A3 A2 A1 A0 READ (RDN = 0) WRITE (WRN = 0) 0 0 0 0 Mode Register A (MR1A, MR2A) Mode Register A (MR1A, MR2A) 0 0 0 1 Status Register A (SRA) Clock Select Register A (CSRA) 0 0 1 0 BRG Extend * Command Register A (CRA) 0 0 1 1 Rx Holding Register A (RHRA) Tx Holding Register A (THRA) 0 1 0 0 Input Port Change Register (IPCR) Aux. Control Register (ACR) 0 1 0 1 Interrupt Status Register (ISR) Interrupt Mask Register (IMR) 0 1 1 0 Counter/Timer Upper Value (CTU) C/T Upper Preset Value (CRUR) 0 1 1 1 Counter/Timer Lower Value (CTL) C/T Lower Preset Value (CTLR) 1 0 0 0 Mode Register B (MR1B, MR2B) Mode Register B (MR1B, MR2B) 1 0 0 1 Status Register B (SRB) Clock Select Register B (CSRB) 1 0 1 0 1 ×/16× Test Command Register B (CRB) 1 0 1 1 Rx Holding Register B (RHRB) Tx Holding Register B (THRB) 1 1 0 0 Use for scratch pad Use for scratch pad 1 1 0 1 Input Ports IP0 to IP6 Output Port Conf. Register (OPCR) 1 1 1 0 Start Counter Command Set Output Port Bits Command 1 1 1 1 Stop Counter Command Reset Output Port Bits Command * See Table 5 for BRG Extended frequencies in this data sheet, and “Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68692 and SCC2698B” in application notes elsewhere in this publication. |
Similar Part No. - SCC2681 |
|
Similar Description - SCC2681 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
