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WM9711 Datasheet(PDF) 47 Page - Wolfson Microelectronics plc |
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WM9711 Datasheet(HTML) 47 Page - Wolfson Microelectronics plc |
47 / 66 page Production Data WM9711L w PD Rev 4.1 April 2004 47 INTERFACE TIMING Test Characteristics: DBVDD = 3.3V, DCVDD = 3.3V, DGND1 = DGND2 = 0V, TA = -25 °C to +85°C, unless otherwise stated. CLOCK SPECIFICATIONS BITCLK SYNC t CLK_HIGH t CLK_LOW t CLK_PERIOD t SYNC_HIGH t SYNC_LOW t SYNC_PERIOD Figure 9 Clock Specifications (50pF External Load) PARAMETER SYMBOL MIN TYP MAX UNIT BITCLK frequency 12.288 MHz BITCLK period tCLK_PERIOD 81.4 ns BITCLK output jitter 750 ps BITCLK high pulse width (Note 1) tCLK_HIGH 36 40.7 45 ns BITCLK low pulse width (Note 1) tCLK_LOW 36 40.7 45 ns SYNC frequency 48 kHz SYNC period tSYNC_PERIOD 20.8 µs SYNC high pulse width tSYNC_HIGH 1.3 µs SYNC low pulse width tSYNC_LOW 19.5 µs Note: 1. Worst case duty cycle restricted to 45/55 DATA SETUP AND HOLD Figure 10 Data Setup and Hold (50pF External Load) Note: 1. Setup and hold times for SDATAIN are with respect to the AC’97 controller, not the WM9711L. |
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