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WM9711 Datasheet(PDF) 46 Page - Wolfson Microelectronics plc |
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WM9711 Datasheet(HTML) 46 Page - Wolfson Microelectronics plc |
46 / 66 page ![]() WM9711L Production Data w PD Rev 4.1 April 2004 46 AC97 DATA AND CONTROL INTERFACE INTERFACE PROTOCOL The WM9711Lhas a single AC’97 interface for both data transfer and control. The AC-Link uses 5 wires: • SDATAIN (pin 8) carries data from the WM9711L to the controller • SDATAOUT (pin 5) carries data from the controller to the WM9711L • BITCLK (pin 6) is a clock, normally generated by the WM9711L crystal oscillator and supplied to the controller. However, BITCLK can also be passed to the WM9711L from an off-chip generator. • SYNC is a synchronization signal generated by the controller and passed to the WM9711L • RESETB resets the WM9711L to its default state CONTROLLER e.g. CPU WM9711L RESETB SDATAIN SDATAOUT BITCLK SYNC 24.576MHz XTAL AC-LINK ANALOGUE INPUTS / OUTPUTS Figure 8 AC-Link Interface (typical case with BITCLK generated by the AC97 codec) The SDATAIN and SDATAOUT signals each carry 13 time-division multiplexed dat a streams (slots 0 to 12). A complete sequence of slots 0 to 12 is referred to as an AC-Link frame, and contains a total of 256 bits. The frame rate is 48kHz. This makes it possible to simultaneously transmit and receive multiple data streams (e.g. audio in, audio out, AUXDAC, GPIO, control) at sample rates up to 48kHz. Detailed information can be found in the AC’97 (Revision 2.2) specification, which can be obtained at www.intel.com/labs/media/audio/ Note: SDATAOUT and SYNC must be held low for when RESETB is applied. These signals must be held low for the entire duration of the RESETB pulse and especially during the low-to-high transition of RESETB. If either is set high during reset the AC'97 device may enter test modes. Information relating to this operation is available in the AC'97 specification or in Wolfson applications note WAN- 0104 available at www.wolfsonmirco.com. |
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