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WM9711 Datasheet(PDF) 44 Page - Wolfson Microelectronics plc

Part # WM9711
Description  LOW POWER AUDIO CODEC FOR PORTABLE APPLICATIONS
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM9711 Datasheet(HTML) 44 Page - Wolfson Microelectronics plc

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WM9711L
Production Data
w
PD Rev 4.1 April 2004
44
Table 32 Extended Power Down Register (Additional to AC’97 Rev 2.2)
Note:
*When disabling a PGA, always ensure that it is muted first.
ADDITIONAL POWER MANAGEMENT:
AUXDAC: see “Auxiliary DAC” section. AUXDAC is OFF by default.
SLEEP MODE
Whenever the PR4 bit (reg. 26h) is set, the AC-Link interface is disabled, and the WM9711L is in
sleep mode. There is in fact a very large number of different sleep modes, depending on the other
control bits. For example, the low-power standby mode described below is a sleep mode. It is
desirable to use sleep modes whenever possible, as this will save power. The following functions do
not require a clock and can therefore operate in sleep mode:
Analogue-to-analogue audio (DACs and ADCs unused), e.g. phone call mode
GPIO and interrupts
Battery alarm / analogue comparators
The WM9711L can awake from sleep mode as a result of
A warm reset on the AC-Link (according to the AC’97 specification)
A signal on a GPIO pin (if the pin is configured as an input, with wake-up enabled – see
“GPIO and Interrupt Control” section)
A virtual GPIO event such as battery alarm, thermal sensor, etc. (see “GPIO and
Interrupt Control” section)
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
15
PD15
0 (ON)
Disables Crystal Oscillator
14
PD14
0 (ON)
Disables left audio DAC
13
PD13
0 (ON)
Disables right audio DAC
12
PD12
0 (ON)
Disables left audio ADC
11
PD11
0 (ON)
Disables right audio ADC
10
PD10
0 (ON)
Disables MICBIAS
9
PD9
0 (ON)
Disables left headphone mixer
8
PD8
0 (ON)
Disables right headphone mixer
7
PD7
0 (ON)
Disables speaker mixer
6
PD6
0 (ON)
Disables MONO_OUT buffer (pin 33) and phone
mixer
5
PD5
0 (ON)
Disables OUT3 buffer (pin 37)
4
PD4
0 (ON)
Disables headphone buffers (HPOUTL/R)
3
PD3
0 (ON)
Disables speaker outputs (LOUT2, ROUT2)
2
PD2
0 (ON)
Disables Line Input PGA (left and right) *
1
PD1
0 (ON)
Disables Phone Input PGA *
24h
Additional
power down
control
0
PD0
0 (ON)
Disables Mic Input PGA (left and right) *
Note: When analogue inputs or outputs are disabled, they are internally connected to VREF
through a large resistor (VREF=AVDD/2 except in OFF mode, when VREF itself is disabled). This
maintains the potential at that node and helps to eliminate pops when the pins are re-enabled.


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