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WM9711 Datasheet(PDF) 43 Page - Wolfson Microelectronics plc |
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WM9711 Datasheet(HTML) 43 Page - Wolfson Microelectronics plc |
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43 / 66 page  Production Data WM9711L w PD Rev 4.1 April 2004 43 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 IRQ INV 0 Inverts the IRQ signal (pin 45) 0: IRQ signal not inverted 1: IRQ signal inverted 58h Additional Functional Control 1 WAKEEN 0 Enables GPIO wake-up 0: Disabled 1: Enabled Table 30 Additional Functionality for GPIO Pins POWER MANAGEMENT The WM9711L includes the standard power down control register defined by the AC’97 specification (register 26h). Additionally, it also allows more specific control over the individual blocks of the device through register 24h. Each particular circuit block is ON when both the relevant bit in register 26h and the relevant bit in register 24h are set to ‘0’. DEFAULT REGISTER ADDRESS BIT LABEL NORMAL PIN 47 ‘HI’ DURING RESET DESCRIPTION 14 PR6 0 (ON) 1 (OFF) Disables HPOUTL, HPOUTR and OUT3 Buffer 13 PR5 0 (ON) 1 (OFF) Disables internal clock 12 PR4 0 (ON) 1 (OFF) Disables AC-link interface (external clock off) 11 PR3 0 (ON) 1 (OFF) Disables VREF, analogue mixers and outputs 10 PR2 0 (ON) 1 (OFF) Disables analogue mixers, LOUT2, ROUT2 (but not VREF) 9 PR1 0 (ON) 1 (OFF) Disables stereo DAC 8 PR0 0 (ON) 1 (OFF) Disables audio ADCs and input Mux 3 REF 1 0 Read-only bit, indicates VREF is ready (inverse of PR2) 2 ANL 1 0 Read-only bit, indicates analogue mixers are ready (inverse of PR3) 1 DAC 1 0 Read-only bit, indicates audio DACs are ready (inverse of PR1) 26h Powerdown/ Status register 0 ADC 1 0 Read-only bit, indicates audio ADCs are ready (inverse of PR0) Table 31 Powerdown and Status Register (Conforms to AC’97 Rev 2.2) As can be seen from the table above, most blocks are ‘ON’ by default. However, if pin 47 (GPIO4/ADA/MASK) is held high during reset, the WM9711L starts up with all blocks powered down by default, saving power. This is achieved by connecting a pull-up resistor (e.g. 100k Ω) from pin 47 to DBVDD. Note that the state of pin 47 during reset only affects register 26h. |
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