MB3793-34A

Document Number: 002-08556 Rev. *A

Page 5 of 26

4. Block Functions

1. Comp.S

detect an abnormality within 1

s when the power is cut or falls abruptly.

2. Output circuit

The output circuit has a comparator to control the reset signal (RESET) output. When the voltage at the CTP pin for setting the

power-on reset hold time exceeds the threshold voltage, resetting is canceled.

Since the reset (RESET) output buffer has the CMOS organization, no pull-up resistor is needed.

3. Pulse generator

The pulse generator generates pulses when the voltage at the CK1 and CK2 input clock pins changes from Low level to High level

(positive-edge trigger) and exceeds the threshold voltage; it sends the clock signal to the watchdog timer.

4. Watchdog timer

The watchdog timer can monitor two clock pulses. Short-circuit the CK1 and CK2 clock pins to monitor a single clock pulse.

5. Logic circuit

Watchdog timer.