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AMPAL22V10 Datasheet(PDF) 4 Page - Advanced Micro Devices |
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AMPAL22V10 Datasheet(HTML) 4 Page - Advanced Micro Devices |
4 / 20 page AMD 2-200 PAL22V10 Family FUNCTIONAL DESCRIPTION The PAL22V10 allows the systems engineer to imple- ment a design on-chip, by opening fuse links to config- ure AND and OR gates within the device, according to the desired logic function. Complex interconnections between gates, which previously required time- consuming layout, are lifted from the PC board and placed on silicon, where they can be easily modified dur- ing prototyping or production. Product terms with all fuses opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. The PAL22V10 has 12 inputs and 10 I/O macrocells. The macrocell (Figure 1) allows one of four potential out- put configurations; registered output or combinatorial I/O, active high or active low (see Figure 2). The configu- ration choice is made according to the user’s design specification and corresponding programming of the configuration bits S0 – S1. Multiplexer controls initially are connected to ground (0) through a programmable fuse, selecting the “0” path through the multiplexer. Pro- gramming the fuse disconnects the control line from GND and it is driven to a high level, selecting the “1” path. The device is produced with a fuse link at each input to the AND gate array, and connections may be selectively removed by applying appropriate voltages to the circuit. Variable Input/Output Pin Ratio The PAL22V10 has twelve dedicated input lines, and each macrocell output can be an I/O pin. Buffers for de- vice inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to VCC or GND. CLK S1 10 11 00 01 AR SP 0 1 I/On S0 S1 S0 Output Configuration 0 0 Registered/Active Low 0 1 Registered/Active High 1 0 Combinatorial/Active Low 1 1 Combinatorial/Active High 0 = Unprogrammed fuse 1 = Programmed fuse 16559C-4 DQ Q Figure 1. Output Logic Macrocell Diagram |
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