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HI-5046A Datasheet(PDF) 1 Page - Intersil Corporation |
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HI-5046A Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 12 page 1 DPDT CMOS Analog Switch HI-5046A/883 This CMOS analog switch offers low-resistance switching performance for analog voltages up to the supply rails and for signal currents up to 70mA. “ON” resistance is low and stays reasonably constant over the full range of operating signal voltage and current. RON remains exceptionally constant for input voltages between +5V and -5V and currents up to 50mA. Switch impedance also changes very little over temperature, particularly between 0°C and +75°C. RON is nominally 25Ω for the HI-5046A/883. This device provides break-before-make switching and is TTL and CMOS compatible for maximum application versatility. Performance is further enhanced by Dielectric Isolation processing which insures latch-free operation with very low input and output leakage currents (0.8nA at +25°C). The HI-5046A/883 also features very low power operation (1.5mW at +25°C). The HI-5046A/883 is available in a 16 Ld CerDIP package and is specified over the temperature range of -55°C to +125°C. Features • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Wide Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Low “On” Resistance . . . . . . . . . . . . . . 25Ω (Typ), 50Ω (Max) • High Current Capability . . . . . . . . . . . . . . . . . . . . . 70mA (Max) • Break-Before-Make Switching - Turn-On Time. . . . . . . . . . . . . . . . . 370ns (Typ), 800ns (Max) - Turn-Off Time . . . . . . . . . . . . . . . .280ns (Typ), 400ns (Max) •No Latch Up • Input MOS Gates are Protected from Electrostatic Discharge • DTL, TTL, CMOS, PMOS Compatible Applications •High Frequency Analog • Sample and Hold • Digital Filters • Operational Amplifier Gain Switching Functional Diagram LOGIC “1” INPUT NOTE: Source and Drain are arbitrarily depicted as Analog Input and Output, respectively. They may be interchanged without affecting performance. Pin Configuration HI1-5046/883 (16 LD CERDIP) TOP VIEW LOGIC “0” INPUT NOTE: Unused pins may be internally connected. Ground all unused pins. Ordering Information PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # HI1-5046A/883 HI1-5046A/883 -55 to +125 16 Ld CerDIP F16.3 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 V- V+ D2 D1 S1 S2 S4 D4 D3 VL VR A S3 S N A P D 12 11 13 14 15 3 4 1 16 8 9 6 5 D1 D2 D4 D3 S1 S3 S4 S2 A V- VR V+ VL TYPICAL SWITCH CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1989, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. May 3, 2012 FN8274.0 |
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