Set CLK = 0 for optimal performance if the external

clock frequency is 1MHz with CLKDIV = 0 or 2MHz with

CLKDIV = 1.

FS1, FS0: (Default = 0, 1) Filter-Selection Bits. These bits

determine the output data rate and the digital-filter cutoff

frequency. See Table 13 for FS1 and FS0 settings.

Recalibrate when the filter characteristics are changed.

Data Register

The data register is a 16-bit register that can be read

and written. Figure 9 shows how to read conversion

results using the data register. A write to the data regis-

ter is not required, but if the data register is written, the

device does not return to its normal state of waiting for

a write to the communications register until all 16 bits

have been written. The 16-bit data word written to the

data register is ignored.

The data from the data register is read through DOUT.

DOUT changes on the falling edge of SCLK and is valid

on the rising edge of SCLK. The data register format is

16-bit straight binary for unipolar mode with zero scale

equal to 0x0000, and offset binary for bipolar mode

with zero scale equal to 0x1000.

16-Bit, Low-Power, 2-Channel,

Sigma-Delta ADC

24

______________________________________________________________________________________

Table 10. Operating-Mode Selection

MD1

MD0

OPERATING MODE

0

0

Normal Mode. Use this mode to perform normal conversions on the selected analog input channel.

01

Self-Calibration Mode. This mode performs self-calibration on the selected channel determined from CH0 and

CH1 selection bits in the communications register (Table 6). Upon completion of self-calibration, the device

returns to normal mode with MD0, MD1 returning to 0, 0. The DRDY output bit goes high when self-calibration is

requested and returns low when the calibration is complete and a new data word is in the data register. Self-

calibration performs an internal zero-scale and full-scale calibration. The analog inputs of the device are shorted

voltage during full-scale calibration. The offset and gain registers for the selected channel are automatically

updated with the calibration data.

10

Zero-Scale System-Calibration Mode. This mode performs zero-scale calibration on the selected channel

determined from CH0 and CH1 selection bits in the communications register (Table 6). The DRDY output bit

goes high when calibration is requested and returns low when the calibration is complete and a new data word

is in the data register. Performing zero-scale calibration compensates for any DC offset voltage present in the

ADC and system. Ensure that the analog input voltage is stable within 1/2 LSB for the duration of the calibration

sequence. The offset register for the selected channel is updated with the zero-scale system-calibration data.

Upon completion of calibration, the device returns to normal mode with MD0, MD1 returning to 0, 0.

11

Full-Scale System-Calibration Mode. This mode performs full-scale system calibration on the selected channel

determined by the CH0 and CH1 selection bits in the communications register. This calibration assigns a full-

scale output code to the voltage present on the selected channel. Ensure that the analog input voltage is stable

within 1/2 LSB for the duration of the calibration sequence. The DRDY output bit goes high during calibration

and returns low when the calibration is complete and a new data word is in the data register. The gain register

for the selected channel is updated with the full-scale system-calibration data. Upon completion of calibration,

the device returns to normal mode with MD0, MD1 returning to 0, 0.

Table 11. PGA Gain Selection

G2

G1

G0

PGA GAIN

00

0

1

00

1

2

01

0

4

01

1

8

10

0

16

10

1

32

11

0

64

1

1

1

128