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MX7705 Datasheet(PDF) 20 Page - Maxim Integrated Products |
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MX7705 Datasheet(HTML) 20 Page - Maxim Integrated Products |
20 / 34 page ![]() Modulator The MX7705 performs analog-to-digital conversions using a single-bit, 2nd-order, switched-capacitor, sigma-delta modulator. The sigma-delta modulation converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal infor- mation. A single comparator within the modulator quan- tizes the input signal at a much higher sample rate than the bandwidth of the input. The MX7705 modulator provides 2nd-order frequency shaping of the quantization noise resulting from the sin- gle-bit quantizer. The modulator is fully differential for maximum signal-to-noise ratio and minimum suscepti- bility to power-supply and common-mode noise. A sin- gle-bit data stream is then presented to the digital filter for processing to remove the frequency-shaped quanti- zation noise. The modulator sampling frequency is fCLKIN / 128, regardless of gain, where fCLKIN (CLKDIV = 0) is the frequency of the signal at CLKIN. Digital Filtering The MX7705 contains an on-chip, digital lowpass filter that processes the 1-bit data stream from the modulator using a SINC3 (sinx/x)3 response. The SINC3 filter has a settling time of three output data periods. Filter Characteristics Figure 6 shows the filter frequency response. The SINC3 characteristic -3dB cutoff frequency is 0.262 times the first-notch frequency. This results in a cutoff frequency of 15.72Hz for a first filter-notch frequency of 60Hz (output data rate of 60Hz). The response shown in Figure 5 is repeated at either side of the digital filter’s sample frequency, fM (fM = 19.2kHz for 60Hz output data rate), and at either side of the related harmonics (2fM, 3fM, etc.). The output data rate for the digital filter corresponds with the positioning of the first notch of the filter’s frequency response. Therefore, for the plot in Figure 6, where the first notch of the filter is 60Hz, the output data rate is 60Hz. The notches of the SINC3 filter are repeated at multiples of the first notch frequency. The SINC3 filter provides an attenua- tion of better than 100dB at these notches. Determine the cutoff frequency of the digital filter by load- ing the appropriate values into the CLK, FS0, and FS1 bits in the clock register (Table 13). Programming a differ- ent cutoff frequency with FS0 and FS1 changes the fre- quency of the notches, but it does not alter the profile of the frequency response. For step changes at the input, allow a settling time before valid data is read. The settling time depends on the output data rate chosen for the filter. The worst- case settling time of a SINC3 filter for a full-scale step input is four times the output data period. By synchro- nizing the step input using FSYNC, the settling time reduces to three times the output data period. If FSYNC is high during the step input, the filter settles in three times the output data period after FSYNC falls low. Analog Filtering The digital filter does not provide any rejection close to the harmonics of the modulator sample frequency. Due to the high oversampling ratio of the MX7705, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. The analog filtering requirements in front of the MX7705 are reduced com- pared to a conventional converter with no on-chip filtering. In addition, the devices provide excellent common-mode rejection of 90db to reduce the common-mode noise sus- ceptibility. Additional filtering prior to the MX7705 eliminates unwanted frequencies the digital filter does not reject. Use additional filtering to ensure that differential noise signals outside the frequency band of interest do not saturate the analog modulator. If passive components are in the path of the analog inputs when the device is in unbuffered mode, ensure the source impedance is low enough (Figure 2) not to introduce gain errors in the system. This significantly limits the amount of passive anti-aliasing filtering that can be applied in front of the MX7705 in unbuffered mode. In buffered mode, large source impedance causes a small DC-offset error, which can be removed by calibration. 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADC 20 ______________________________________________________________________________________ -160 -120 -140 -100 -80 -60 -20 -40 0 0 406080 20 100 120 140 160 180 200 FREQUENCY (Hz) fCLKIN = 2.4576MHz CLK = 1 FS1 = 0 FS0 = 1 fN = 60Hz Figure 6. Frequency Response of the SINC3 Filter (Notch at 60Hz) |
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