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IDT71V3557S Datasheet(PDF) 13 Page - Integrated Device Technology |
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IDT71V3557S Datasheet(HTML) 13 Page - Integrated Device Technology |
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13 / 28 page  6.42 IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges 13 Read Operation with Clock Enable Used (1) Write Operation with Clock Enable Used (1) NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals. Cycle Address R/W ADV/LD CE1(2) CEN BW x OE I/O Comments nA0 H L L L XXX AddressA0 and Control meet setup n+1 X X X X H X X X Clock n+1 Ignored n+2 A1 HL L L X L Q0 Address A0 Read out, Load A1 n+3 X X X XH XL Q0 Clock Ignored. Data Q0 is on the bus. n+4 X X X XH XL Q0 Clock Ignored. Data Q0 is on the bus. n+5 A2 HL L L X L Q1 Address A1 Read out, Load A2 n+6 A3 HL L L X L Q2 Address A2 Read out, Load A3 n+7 A4 HL L L X L Q3 Address A3 Read out, Load A4 5282 tbl 17 Cycle Address R/W ADV/LD CE1(2) CEN BW x OE I/O Comments nA0 L L L L L X X Address A0 and Control meet setup. n+1 X X X X H X X X Clock n+1 Ignored. n+2 A1 L L LLL X D0 Write data D0, Load A1. n+3 X X X X H X X X Clock Ignored. n+4 X X X X H X X X Clock Ignored. n+5 A2 L L LLL X D1 Write Data D1, Load A2 n+6 A3 L L LLL X D2 Write Data D2, Load A3 n+7 A4 L L LLL X D3 Write Data D3, Load A4 5282 tbl 18 |
Similar Part No. - IDT71V3557S_09 |
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Similar Description - IDT71V3557S_09 |
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