APRIL 2011

DSC-5294/07

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©2011 Integrated Device Technology, Inc.

Pin Description Summary

Description

The IDT71V2546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM. It is designed to eliminate dead bus cycles when

turning the bus around between reads and writes, or writes and reads.

Features

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(3.8 ns Clock-to-Data Access)

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cycles

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need to control OE

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signal registers for fully pipelined applications

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flatpack (TQFP) and 119 ball grid array (BGA)

IDT71V2546S/XS

128K x 36

3.3V Synchronous ZBT™ SRAM

2.5V I/O, Burst Counter

Pipelined Outputs

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle, and two cycles later the associated data cycle occurs, be it read

or write.

The IDT71V2546 contains data I/O, address and control signal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

AClockEnable(CEN)pinallowsoperationoftheIDT71V2546tobe

suspended as long as necessary. All synchronous inputs are ignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

to deselect the device when desired. If any one of these three are not

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

The data bus will tri-state two cycles after chip is deselected or a write is

initiated.

TheIDT71V2546hasanon-chipburstcounter.Intheburstmode,the

IDT71V2546 can provide four cycles of data for a single address

presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe

LBO

inputpin.TheLBOpinselectsbetweenlinearandinterleavedburst

sequence. The ADV/LD signal is used to load a new external address

(ADV/LD = LOW) or increment the internal burst counter (ADV/LD =

HIGH).

TheIDT71V2546SRAMutilizeIDT's latesthigh-performanceCMOS

process and is packaged in a JEDEC standard 14mm x 20mm 100-pin

thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA).

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