IDT71V2546S_11 datasheet(7/21 Pages) IDT

Part #	IDT71V2546S

Description	3.3V Synchronous ZBT SRAM

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Manufacturer	IDT [Integrated Device Technology]

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6.42

IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM

with 2.5V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

7

Synchronous Truth Table(1)

Partial Truth Table for Writes(1)

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will

tri-state two cycles after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/

Os remains unchanged.

5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

7. Q - Data read from the device, D - data written to the device.

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

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