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IDT71V2546S Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT71V2546S Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 21 page 6.42 IDT71V2546 128K x 36, 3.3V Synchronous ZBT™ SRAM with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 3 Functional Block Diagram Clk DQ DQ DQ Address A [0:16] Control Logic Address Control DI DO 5294 drw 01a Clock Data I/O [0:31], I/O P[1:4] D Q Output Register Mux Sel Gate O E C E 1, CE2, C E2 R/W C E N ADV/LD B W x LB O 128Kx36 BIT MEMORY ARRAY Recommended DC Operating Conditions NOTES: 1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle. 2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle. l o b m y Sr e t e m a r a P. n i M. p y T. x a Mt i n U V D D e g a tl o V y l p p u S e r o C5 3 1 . 33 . 35 6 4 . 3V V Q D D e g a tl o V y l p p u S O /I5 7 3 . 25 . 25 2 6 . 2V V S S e g a tl o V y l p p u S0 0 0 V V H I s t u p n I - e g a tl o V h g i H t u p n I7 . 1 _ _ _ _ V D D 3 . 0 +V V H I e g a tl o V h g i H t u p n I- O /I7 . 1 _ _ _ _ V Q D D 3 . 0 + ) 2 ( V V L I e g a tl o V w o L t u p n I3 . 0 - ) 1 ( _ _ _ _ 7 . 0V 3 0 l b t 4 9 2 5 |
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