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IDT71V546S Datasheet(PDF) 14 Page - Integrated Device Technology |
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IDT71V546S Datasheet(HTML) 14 Page - Integrated Device Technology |
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14 / 21 page  14 IDT71V546, 128K x 36, 3.3V Synchronous SRAM with ZBT ™ ™ ™ ™ ™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges) NOTES: 1. tF = 1/tCYC. 2. Measured as HIGH above 2.0V and LOW below 0.8V. 3. Transition is measured ±200mV from steady-state. 4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested. 5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 2 ns faster than tCLZ (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V). Symbol Parameter 71V546S133 71V546S117 71V546S100 Unit Min. Max. Min. Max. Min. Max. Clock Parameters tCYC Clock Cycle Time 7.5 ____ 8.5 ____ 10 ____ ns tF(1) Clock Frequency ____ 133 ____ 117 ____ 100 MHz tCH(2) Clock High Pulse Width 2.5 ____ 3 ____ 3.5 ____ ns tCL(2) Clock Low Pulse Width 2.5 ____ 3 ____ 3.6 ____ ns Output Parameters tCD Clock High to Valid Data ____ 4.2 ____ 4.5 ____ 5ns tCDC Clock High to Data Change 1.5 ____ 1.5 ____ 1.5 ____ ns tCLZ(3,4,5) Clock High to Output Active 1.5 ____ 1.5 ____ 1.5 ____ ns tCHZ(3,4,5) Clock High to Data High-Z 1.5 3.5 1.5 3.5 1.5 3.5 ns tOE Output Enable Access Time ____ 4.2 ____ 4.5 ____ 5ns tOLZ(3,4) Output Enable Low to Data Active 0 ____ 0 ____ 0 ____ ns tOHZ(3.4) Output Enable High to Data High-Z ____ 3.5 ____ 3.5 ____ 3.5 ns Setup Times tSE Clock Enable Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns tSA Address Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns tSD Data in Setup Time 1.7 ____ 1.7 ____ 2.0 ____ ns tSW Read/Write (R/W) Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns tSADV Advance/Load (ADV/LD) Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns tSC Chip Enable/Select Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns tSB Byte Write Enable (BWx) Setup Time 2.0 ____ 2.0 ____ 2.2 ____ ns Hold Times tHE Clock Enable Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHD Data in Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHW Read/Write (R/W) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHADV Advance/Load (ADV/LD) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHC Chip Enable/Select Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHB Byte Write Enable (BWx) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 3821 tbl 23 |
Similar Part No. - IDT71V546S_08 |
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Similar Description - IDT71V546S_08 |
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