IDT71V546S_08 datasheet(11/21 Pages) IDT

Part #	IDT71V546S

Description	3.3V Synchronous SRAM

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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11 / 21 page

6.42

11

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT

™

™ Feature, Burst Counter and Pipelined Outputs

Commercial and Industrial Temperature Ranges

NOTE:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Read Operation With Clock Enable Used(1)

NOTE:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Write Operation with Clock Enable Used(1)

Cycle

Address

R/W

ADV/LD

CE(2)

CEN

BWx

OE

I/O

Comments

n

A0

H

L

X

Address and Control meet setup

n+1

X

H

X

Clock n+1 Ignored

n+2

A1

H

L

XXX

Clock Valid

n+3

X

H

X

L

Q0

Clock Ignored. Data Q0 is on the bus

n+4

X

H

X

L

Q0

Clock Ignored. Data Q0 is on the bus

n+5

A2

H

L

X

L

Q0

Address A0 Read out (but trans.)

n+6

A3

H

L

X

L

Q1

Address A1 Read out (bus trans.)

n+7

A4

H

L

X

L

Q2

Address A2 Read out (bus trans.)

3821 tbl 16

Cycle

Address

R/W

ADV/LD

CE(2)

CEN

BWx

OE

I/O

Comments

n

A0

L

X

Address and Control meet setup

n+1

X

H

X

Clock n+1 Ignored

n+2

A1

L

LLL

X

Clock Valid

n+3

X

H

XXX

Clock Ignored

n+4

X

H

XXX

Clock Ignored

n+5

A2

L

LLL

X

D0

Write data D0

n+6

A3

L

LLL

X

D1

Write data D1

n+7

A4

L

LLL

X

D2

Write data D2

3821 tbl 17

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