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IDT71V546S Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V546S Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 21 page  1 ©2008 Integrated Device Technology, Inc. OCTOBER 2008 DSC-3821/05 ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc. Pin Description Summary Description The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAM organized as 128K x 36 bits. It is designed to eliminate dead bus cycles when turning the bus around between reads andwrites,orwritesandreads. ThusithasbeengiventhenameZBTTM, or Zero Bus Turn-around. Address and control signals are applied to the SRAM during one Features ◆ ◆ ◆ ◆ ◆ 128K x 36 memory configuration, pipelined outputs ◆ ◆ ◆ ◆ ◆ Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ◆ ◆ ◆ ◆ ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ ◆ ◆ ◆ ◆ Internally synchronized registered outputs eliminate the need to control OE ◆ ◆ ◆ ◆ ◆ Single R/W (READ/WRITE) control pin ◆ ◆ ◆ ◆ ◆ Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications ◆ ◆ ◆ ◆ ◆ 4-word burst capability (interleaved or linear) ◆ ◆ ◆ ◆ ◆ Individual byte write (BW1 - BW4) control (May tie active) ◆ ◆ ◆ ◆ ◆ Three chip enables for simple depth expansion ◆ ◆ ◆ ◆ ◆ Single 3.3V power supply (±5%) ◆ ◆ ◆ ◆ ◆ Packaged in a JEDEC standard 100-pin TQFP package clock cycle, and two cycles later its associated data cycle occurs, be it read or write. TheIDT71V546containsdataI/O,addressandcontrolsignalregis- ters. Output enable is the only asynchronous signal and can be used to disabletheoutputsatanygiventime. A Clock Enable (CEN) pin allows operation of the IDT71V546 to be suspended as long as necessary. All synchronous inputs are ignored whenCENishighandtheinternaldeviceregisterswillholdtheirprevious values. Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser todeselectthedevicewhendesired. Ifanyoneofthesethreeisnotactive whenADV/LDislow,nonewmemoryoperationcanbeinitiatedandany burst that was in progress is stopped. However, any pending data transfers(readsorwrites)willbecompleted. Thedatabuswilltri-statetwo cyclesafterthechipisdeselectedorawriteinitiated. TheIDT71V546hasanon-chipburstcounter. Intheburstmode,the IDT71V546canprovidefourcyclesofdataforasingleaddresspresented totheSRAM. TheorderoftheburstsequenceisdefinedbytheLBOinput pin. TheLBOpinselectsbetweenlinearandinterleavedburstsequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH). TheIDT71V546SRAMutilizesIDT'shigh-performance,high-volume 3.3V CMOS process, and is packaged in a JEDEC standard 14mm x 20mm100-pinthinplasticquadflatpack(TQFP)forhighboarddensity. IDT71V546S/XS 128K x 36, 3.3V Synchronous SRAM with ZBT ™ ™ ™ ™ ™ Feature, Burst Counter and Pipelined Outputs A0 - A16 Address Inputs Input Synchronous CE1 , CE2, CE2 Three Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/LD Advance Burst Address / Load New Address Input Synchronous LBO Linear / Interleaved Burst Order Input Static I/O0 - I/O31, I/OP1 - I/OP4 Data Input/Output I/O Synchronous VDD 3.3V Power Supply Static VSS Ground Supply Static 3821 tbl 01 |
Similar Part No. - IDT71V546S_08 |
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Similar Description - IDT71V546S_08 |
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